Hello Nico,
My patch to ./roda/rk9/romstage.c
--- ./rk9_orig/romstage.c 2014-02-14 18:26:39.000000000 +0400 +++ ./rk9_patch/romstage.c 2014-02-14 18:36:24.859508133 +0400 @@ -47,10 +47,14 @@ /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT, WLAN, ~ANTMUX, ~GPIO12, ~SUSPWR, SMBALERT) */ - outl(0x00000800, DEFAULT_GPIOBASE + 0x0c); + //outl(0x00000800, DEFAULT_GPIOBASE + 0x0c);
+ outl(0xe6c8cbff, DEFAULT_GPIOBASE + 0x0c); /* Disable blink [31:0]. */ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); + + outl(0x00080000, DEFAULT_GPIOBASE + 0x20); + /* Set input inversion [31:0]. */ outl(0x00000182, DEFAULT_GPIOBASE + 0x2c);
@@ -61,7 +65,8 @@ /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO, DMITERM, TXT, ~CLKSATA, GPS, AUDIO) */ - outl(0x10020042, DEFAULT_GPIOBASE + 0x38); + //outl(0x10020042, DEFAULT_GPIOBASE + 0x38); + outl(0x1cfffff2, DEFAULT_GPIOBASE + 0x38); }
static void early_lpc_setup(void) @@ -74,6 +79,30 @@ pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */ pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03); + /* Enable decoding of 0x600-0x61f through lpc. */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x001f0601); + /* Enable decoding COM3 and COM4 */ + pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c02e1); + pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x001c03e1); +} + +static inline void pnp_enter_ext_func_mode(device_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +static void pnp_write_register(device_t dev, int reg, int val) +{ + unsigned int port = dev >> 8; + outb(reg, port); + outb(val, port+1); }
static void default_superio_gpio_setup(void) @@ -87,45 +116,88 @@ GP1 GP2 GP3 GP4 fd 17 88 14 */ - const device_t sio = PNP_DEV(0x2e, 0); + + device_t dev;
- /* Enter super-io's configuration state. */ - pnp_enter_conf_state(sio); - - /* Set lpc47n227's runtime register block's base address. */ - pnp_write_config(sio, 0x30, 0x600 >> 4); - - /* Set GP23 to alternate function. */ - pnp_write_config(sio, 0x33, 0x40); - - /* Set GP30 - GP37 to output mode: COM control */ - pnp_write_config(sio, 0x35, 0xff); - - /* Set GP45 - GP47 to output mode. */ - pnp_write_config(sio, 0x37, 0xe0); - - /* Set nIO_PME to open drain. */ - pnp_write_config(sio, 0x39, 0x80); - - /* Exit configuration state. */ - pnp_exit_conf_state(sio); - - - /* Enable decoding of 0x600-0x60f through lpc. */ - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601); + dev=PNP_DEV(0x2e, 0x00);
+ pnp_enter_ext_func_mode(dev); + pnp_write_register(dev, 0x01, 0x9c); // Extended Parport modes + pnp_write_register(dev, 0x02, 0x00); // UART power on + pnp_write_register(dev, 0x03, 0x72); // Floppy + pnp_write_register(dev, 0x04, 0x00); // EPP + SPP + pnp_write_register(dev, 0x14, 0x02); // Floppy + pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy + pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base + pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base + pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base + pnp_write_register(dev, 0x26, (2 << 4) | 0x0f); // FDC + PP DMA + pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA + pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ + /* These are the SMI status registers in the SIO: */ + pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + + pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR + pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL + pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR + pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL + pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR + pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL + pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR + pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL + pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL + + pnp_exit_ext_func_mode(dev); + + dev=PNP_DEV(0x4e, 0x00); + + pnp_enter_ext_func_mode(dev); + pnp_write_register(dev, 0x01, 0x98); // Extended Parport modes + pnp_write_register(dev, 0x02, 0x00); // UART power on + pnp_write_register(dev, 0x03, 0x70); // Floppy + pnp_write_register(dev, 0x04, 0x01); // EPP + SPP + pnp_write_register(dev, 0x14, 0x02); // Floppy + //pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy + //pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base + pnp_write_register(dev, 0x24, (0x3e8 >> 2)); // UART3 base + pnp_write_register(dev, 0x25, (0x2e8 >> 2)); // UART4 base + pnp_write_register(dev, 0x26, (0x0f << 4) | 0x0f); // FDC + PP DMA + //pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA + pnp_write_register(dev, 0x28, (10 << 4) | 5); // UART3,4 IRQ + /* These are the SMI status registers in the SIO: */ + pnp_write_register(dev, 0x30, (0x610 >> 4)); // Runtime Register Block Base + + pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR + pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL + pnp_write_register(dev, 0x33, 0x00); // GPIO2 DIR + pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL + pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR + pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL + pnp_write_register(dev, 0x37, 0x00); // GPIO4 DIR + pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL + pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL + + + pnp_exit_ext_func_mode(dev); + /* Set GPIO output values: */ + outb(0xfd, 0x600 + 0xb + 1); /* GP10 - GP17 */ + outb(0x17, 0x600 + 0xb + 2); /* GP20 - GP27 */ outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */ outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ + + outb(0xff, 0x610 + 0xb + 1); /* GP10 - GP17 */ + outb(0x1f, 0x610 + 0xb + 2); /* GP20 - GP27 */ + outb(0x88, 0x610 + 0xb + 3); /* GP30 - GP37 */ + outb(0xff, 0x610 + 0xb + 4); /* GP40 - GP47 */ }
void main(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; - int cbmem_initted; u16 reg16; - + /* basic northbridge setup, including MMCONF BAR */ gm45_early_init();
@@ -136,8 +208,10 @@ i82801ix_early_init(); early_lpc_setup(); default_superio_gpio_setup(); - lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + //lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); console_init(); + printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); @@ -184,12 +258,11 @@
init_iommu();
- cbmem_initted = !cbmem_recovery(0); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_initted) { + if (s3resume && cbmem_reinit() { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
Thank you Best regards, Dmitry Bagryanskiy