joe@smittys.pointclark.net wrote:
Is SPD detection done though the memory controller or through the superIO via the SMBUS (i2c)?
Through SMBus, on the southbridge. I'm not positive about Intel's setup, but with Via you have to first set up a couple registers on the southbridge to set the SMBus port address, then stick in a few functions for reading spd data (see smbus_read_byte and smbus_enable in southbridge/<model>/early_smbus.c). Here's some nice writeups on SPD:
DDR2: http://www.simmtester.com/page/news/showpubnews.asp?num=139 DDR: http://www.simmtester.com/page/news/showpubnews.asp?num=101 SDRAM: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf (sorry, no nice simple writeup available, but check out the other ones for pointers. This also isn't the best datasheet on it, but I'm too lazy to go diving into the JEDEC site again)
The picture on the first two links shows the SPD rom on a memory module, note it's not part of the actual memory and connects to pins which connect to the southbridge, so it can be read before ram init ever occurs, or even during ram init, without disturbing things. The BIOS Porting Guides I've read usually recommend to do ram init with safe values (minimum size for all banks, extremely loose timings) before attempting to read the spd, but most factory BIOSs don't have the power of cache-as-ram :D Since ram init takes only but a few milliseconds, you can do it that way if you want, but my way of thinking is why do anything twice if you don't have to?
-Corey