[LinuxBIOS] Question about raminit.c

Quick question about raminit.c

Seems like it sets register values just enough to get going (function  
sdram_set_registers) and then detects spd on the memory and the resets  
the register values according to the memory. Correct?

Wouldn't make sense to just detect the spd values first and then set  
the registers??

Or, does it have to set the register values just enough to get going  
so it can then detect spd?

Thanks - Joe

[Peter Stuge]

On Fri, May 04, 2007 at 01:37:20AM -0400, [e-mail] wrote:
> Or, does it have to set the register values just enough to get
> going so it can then detect spd?

Probably true, the SPD EEPROM is on the RAM module itself so at least
some part of the memory controller may need to be working to reach
it.

//Peter

Is SPD detection done though the memory controller or through the  
superIO via the SMBUS (i2c)?

Thanks - Joe

Quoting Peter Stuge :
> On Fri, May 04, 2007 at 01:37:20AM -0400, [e-mail] wrote:
> > Or, does it have to set the register values just enough to get
> > going so it can then detect spd?
>
> Probably true, the SPD EEPROM is on the RAM module itself so at least
> some part of the memory controller may need to be working to reach
> it.
>
> //Peter

[Peter Stuge]

On Fri, May 04, 2007 at 01:46:33AM -0400, [e-mail] wrote:
> Is SPD detection done though the memory controller or through the
> superIO via the SMBUS (i2c)?

The smbus is on the southbridge, yeah, not the memory controller.

Power would have to be controlled by the memory controller though,
maybe that's it.

//Peter

[Corey Osgood]

Peter Stuge wrote:
> Power would have to be controlled by the memory controller though,
> maybe that's it.

Not in my tests, on the cn700/vt8237r i can dump the contents of the spd
without ever touching the northbridge. Intel and server stuff might be
different though

-Corey

[Corey Osgood]

[e-mail] wrote:
> Is SPD detection done though the memory controller or through the  
> superIO via the SMBUS (i2c)?

Through SMBus, on the southbridge. I'm not positive about Intel's setup,
but with Via you have to first set up a couple registers on the
southbridge to set the SMBus port address, then stick in a few functions
for reading spd data (see smbus_read_byte and smbus_enable in
southbridge/<model>/early_smbus.c). Here's some nice writeups on SPD:

DDR2:  http://www.simmtester.com/page/news/showpubnews.asp?num=139
DDR:   http://www.simmtester.com/page/news/showpubnews.asp?num=101
SDRAM: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf (sorry,
no nice simple writeup available, but check out the other ones for
pointers. This also isn't the best datasheet on it, but I'm too lazy to
go diving into the JEDEC site again)

The picture on the first two links shows the SPD rom on a memory module,
note it's not part of the actual memory and connects to pins which
connect to the southbridge, so it can be read before ram init ever
occurs, or even during ram init, without disturbing things. The BIOS
Porting Guides I've read usually recommend to do ram init with safe
values (minimum size for all banks, extremely loose timings) before
attempting to read the spd, but most factory BIOSs don't have the power
of cache-as-ram :D Since ram init takes only but a few milliseconds, you
can do it that way if you want, but my way of thinking is why do
anything twice if you don't have to?

-Corey

If the SPD register settings can be read through the SMBUS than it  
seems a little silly to set any of the memory controller registers  
first. Exactly my point Corey, why do anything twice if you don't have  
to. raminit.c seems to set the memory controller registers first,  
detect SPD, calculate, and re-set the memory controller registers  
again. If we cut to the chase and just detect SPD,calculate, and set  
the memory controller registers, it could speed things up alot more.  
:) Thoughts?

Thanks - Joe

Quoting Corey Osgood :
> [e-mail] wrote:
> > Is SPD detection done though the memory controller or through the
> > superIO via the SMBUS (i2c)?
>
> Through SMBus, on the southbridge. I'm not positive about Intel's setup,
> but with Via you have to first set up a couple registers on the
> southbridge to set the SMBus port address, then stick in a few functions
> for reading spd data (see smbus_read_byte and smbus_enable in
> southbridge/<model>/early_smbus.c). Here's some nice writeups on SPD:
>
> DDR2:  http://www.simmtester.com/page/news/showpubnews.asp?num=139
> DDR:   http://www.simmtester.com/page/news/showpubnews.asp?num=101
> SDRAM: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf (sorry,
> no nice simple writeup available, but check out the other ones for
> pointers. This also isn't the best datasheet on it, but I'm too lazy to
> go diving into the JEDEC site again)
>
> The picture on the first two links shows the SPD rom on a memory module,
> note it's not part of the actual memory and connects to pins which
> connect to the southbridge, so it can be read before ram init ever
> occurs, or even during ram init, without disturbing things. The BIOS
> Porting Guides I've read usually recommend to do ram init with safe
> values (minimum size for all banks, extremely loose timings) before
> attempting to read the spd, but most factory BIOSs don't have the power
> of cache-as-ram :D Since ram init takes only but a few milliseconds, you
> can do it that way if you want, but my way of thinking is why do
> anything twice if you don't have to?
>
> -Corey