Re: [LinuxBIOS] [PATCH] Add support for the Asus A8V-E SE motherboard

30 Oct 2007

On Sat, Oct 27, 2007 at 08:49:32PM +0200, Rudolf Marek wrote:
...
I'm attaching the patch to add support for Asus A8V-E SE motherboard.
Signed-off-by: Rudolf Marek r.marek@assembler.cz
I tried to clean the code as much as possible, but I left there the CMOS 
setting, cause removing the file will cause a lot of trouble and I cannot 
figure out how to fix that. Same applies for Config.lb and Option.lb files.
No problem, but please see below for some comments.
Also, now that NB and SB are committed, please re-check if the board
still builds fine and if the created code actually runs ok on the hardware.
...
I fixed the ACPI dsdt build, and FADT table uses static resources defined 
in SB, so it will be always consistent with SB implementation.
Yep, this is great!
...
Index: src/mainboard/asus/a8v-e_se/fadt.c

--- src/mainboard/asus/a8v-e_se/fadt.c	(revision 0)
+++ src/mainboard/asus/a8v-e_se/fadt.c	(revision 0)
@@ -0,0 +1,151 @@
+/*


ACPI - create the Fixed ACPI Description Tables (FADT)



(C) Copyright 2004 Nick Barker nick.barker9@btinternet.com



(C) Copyright 2007 Rudolf Marek r.marek@assembler.cz







This program is free software; you can redistribute it and/or



modify it under the terms of the GNU General Public License as



published by the Free Software Foundation; either version 2 of



the License, or (at your option) any later version.







This program is distributed in the hope that it will be useful,



but WITHOUT ANY WARRANTY; without even the implied warranty of



MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the



GNU General Public License for more details.







You should have received a copy of the GNU General Public License



along with this program; if not, write to the Free Software



Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,



MA 02110-1301 USA


*/


+#include <string.h>
+#include <arch/acpi.h>
+#include <../../../southbridge/via/vt8237r/vt8237r.h>
Why this? Doesn't the usual method work?
#include "southbridge/via/vt8237r/vt8237r.h"
...



+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{

acpi_header_t *header = &(fadt->header);

memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 1;
memcpy(header->oem_id, "LXBIOS", 6);

"LinuxBIOS" as string? How long can the ID become?
...

memcpy(header->oem_table_id, "LXBACPI ", 8);
memcpy(header->asl_compiler_id, "LXB", 8);

Same here. How long?
...

header->asl_compiler_revision = 0;

fadt->firmware_ctrl = facs;
fadt->dsdt = dsdt;
fadt->preferred_pm_profile = 0;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->acpi_enable = 0;
fadt->acpi_disable = 0;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0x0;

fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = 0x0;
fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8;
fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20;
fadt->gpe1_blk = 0x0;

fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 90;
fadt->p_lvl3_lat = 900;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 0;
fadt->duty_width = 1;	//??
fadt->day_alrm = 0x7d;
fadt->mon_alrm = 0x7e;
fadt->century = 0x32;
/* fixme 5 - 10 */
fadt->iapc_boot_arch = 0x1;
/* fixme */
fadt->flags = 0x4a5;

fadt->reset_reg.space_id = 0;
fadt->reset_reg.bit_width = 0;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0x0;
fadt->reset_reg.addrh = 0x0;

fadt->reset_value = 0;
fadt->x_firmware_ctl_l = facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = dsdt;
fadt->x_dsdt_h = 0;

fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 4;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = VT8237R_ACPI_IO_BASE;
fadt->x_pm1a_evt_blk.addrh = 0x0;

fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;

fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 2;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = VT8237R_ACPI_IO_BASE + 0x4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;

fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;

fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = 0x0;
fadt->x_pm2_cnt_blk.addrh = 0x0;

fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 4;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = VT8237R_ACPI_IO_BASE + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;

fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 0;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = VT8237R_ACPI_IO_BASE + 0x20;
fadt->x_gpe0_blk.addrh = 0x0;

fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;

header->checksum =
   acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));



Let's commit this, but can it be changed later?
This all looks very similar, maybe a 'static const struct ...' table
with all the numbers, and a small loop to set the entries would
be possible?
Similar example:
http://tracker.linuxbios.org/trac/LinuxBIOS/browser/trunk/LinuxBIOSv2/src/so...
...
+}
Index: src/mainboard/asus/a8v-e_se/Config.lb
===================================================================
--- src/mainboard/asus/a8v-e_se/Config.lb	(revision 0)
+++ src/mainboard/asus/a8v-e_se/Config.lb	(revision 0)
@@ -0,0 +1,273 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu yinghailu@amd.com for AMD.
+##
+## Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##



+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##

if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE   = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end


+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD     = 1



+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )



+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )



+arch i386 end



+##
+## Build the objects we have code for in this directory.
+##



+driver mainboard.o



+if HAVE_ACPI_TABLES

   object acpi_tables.o


   object fadt.o


makerule dsdt.c
depends "$(MAINBOARD)/dsdt.asl"


action  "iasl -tc $(MAINBOARD)/dsdt.asl"


action  "mv dsdt.hex dsdt.c"


end
   object ./dsdt.o



+end



+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+if USE_DCACHE_RAM


if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o


        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"


   		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"


end


else
makerule ./cache_as_ram_auto.inc


   		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"


        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"


        action "perl -e 's/.rodata/.rom.data/g' -pi $@"


   		action "perl -e 's/.text/.section .rom.text/g' -pi $@"


end


end


+end



+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##



+if USE_FALLBACK_IMAGE

   mainboardinit cpu/x86/16bit/entry16.inc


   ldscript /cpu/x86/16bit/entry16.lds


mainboardinit southbridge/via/k8t890/romstrap.inc
ldscript /southbridge/via/k8t890/romstrap.lds


+end



+mainboardinit cpu/x86/32bit/entry32.inc



+if USE_DCACHE_RAM

   if CONFIG_USE_INIT


           ldscript /cpu/x86/32bit/entry32.lds


   end



   if CONFIG_USE_INIT


           ldscript /cpu/amd/car/cache_as_ram.lds


   end



+end




+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##



+if USE_FALLBACK_IMAGE

mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds

+else

mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds

+end



+if USE_DCACHE_RAM

##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc

+end



+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###



+if USE_FALLBACK_IMAGE

if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds


end

+end




+##
+## Setup RAM
+##
+if USE_DCACHE_RAM


if CONFIG_USE_INIT
initobject cache_as_ram_auto.o


else
mainboardinit ./cache_as_ram_auto.inc


end

+end



+##
+## Include the secondary Configuration files 
+##
+if CONFIG_CHIP_NAME

config chip.h

+end



+chip northbridge/amd/amdk8/root_complex

   device apic_cluster 0 on


           chip cpu/amd/socket_939


                   device apic 0 on end


           end


   end



  device pci_domain 0 on


          chip northbridge/amd/amdk8 #mc0


                  device pci 18.0 on #  northbridge


                          #  devices on link 0, link 0 == LDT 0


                          chip southbridge/via/vt8237r


			#both IDE channels


			register "ide0_enable" = "1"


			register "ide1_enable" = "1"


			#both cables are 80pin


			register "ide0_80pin_cable" = "1"


			register "ide1_80pin_cable" = "1"


			#enables the functions of SB


			register "fn_ctrl_lo" = "0"


			register "fn_ctrl_hi" = "0xad"



                                  device pci 0.0 on end   # HT


                                  device pci f.1 on end   # IDE


                                  device pci 11.0 on # LPC


                                           chip drivers/generic/generic #dimm 0-0-0


                                                   device i2c 50 on end  


                                           end              


                                           chip drivers/generic/generic #dimm 0-0-1


                                                   device i2c 51 on end


                                           end     


                                           chip drivers/generic/generic #dimm 0-1-0


                                                   device i2c 52 on end


                                           end             


                                           chip drivers/generic/generic #dimm 0-1-1


                                                   device i2c 53 on end


                                           end              



                                          chip superio/winbond/w83627ehg


                                                  device pnp 2e.0 on #  Floppy


                                                          io 0x60 = 0x3f0


                                                          irq 0x70 = 6


                                                          drq 0x74 = 2


                                                  end


                                                  device pnp 2e.1 off #  Parallel Port


                                                          io 0x60 = 0x378


                                                          irq 0x70 = 7


                                                  end


                                                  device pnp 2e.2 on #  Com1


                                                          io 0x60 = 0x3f8


                                                          irq 0x70 = 4


                                                  end


                                                  device pnp 2e.3 off #  Com2


                                                          io 0x60 = 0x2f8


                                                          irq 0x70 = 3


                                                  end


                                                  device pnp 2e.5 off #keyb OFF


                                                  end


                                                  device pnp 2e.6 off #  SERIAL_FALSH


                                                          io 0x60 = 0x100


                                                  end


                                                  device pnp 2e.7 off #  GAME_MIDI_GIPO1


                                                         # io 0x60 = 0x220


                                                         # io 0x62 = 0x300


                                                         # irq 0x70 = a


                                                  end


                                                  device pnp 2e.8 off end #  WDTO_PLED


                                                  device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5 0x30 0x9


								#GPIO 5 and 2 active


						#0xe0 = de


						#0xe1 = 01


						#0xe2 = 00


						#0xe3 = 03


						#0xe4 = a4


						#0xe5 = 00



                                                  device pnp 2e.a off end #  ACPI


                                                  device pnp 2e.b on #  HW Monitor


                                                          io 0x60 = 0x290


                                                          irq 0x70 = 0


                                                  end



Do you have 'superiotool -dV' output from the original BIOS so we can
check some of the commented values?
...

                                          end #end SIO


                                  end #end 11



                                  device pci 12.0 off end # VIA LAN



Why off? Is this the integrated SB LAN or another onboard PCI device?
...

                          end



                          chip southbridge/via/k8t890


		end



                  end #  device pci 18.0


                  device pci 18.1 on end


                  device pci 18.2 on end


                  device pci 18.3 on end


          end #mc0



  end # pci_domain




+end # root_complex
Index: src/mainboard/asus/a8v-e_se/mptable.c
===================================================================
--- src/mainboard/asus/a8v-e_se/mptable.c	(revision 0)
+++ src/mainboard/asus/a8v-e_se/mptable.c	(revision 0)
@@ -0,0 +1,161 @@
+/*


This file is part of the LinuxBIOS project.







Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz







This program is free software; you can redistribute it and/or modify



it under the terms of the GNU General Public License v2 as published by



the Free Software Foundation.







This program is distributed in the hope that it will be useful,



but WITHOUT ANY WARRANTY; without even the implied warranty of



MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the



GNU General Public License for more details.







You should have received a copy of the GNU General Public License



along with this program; if not, write to the Free Software



Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA


*/


+#include <arch/smp/mpspec.h>
+#include <string.h>
+#include <stdint.h>



+#include <../../../southbridge/via/vt8237r/vt8237r.h>
+#include <../../../southbridge/via/k8t890/k8t890.h>



+void *smp_write_config_table(void *v)
+{

   static const char sig[4] = "PCMP";



...

   static const char oem[8] = "LNXI    ";



Should be "ASUS    " probably, but I don't think that can break anything,
it's more a cosmetic issue AFAIK.
...

   static const char productid[12] = "A8V-E SE    ";


   struct mp_config_table *mc;


unsigned int conforms = 0;
int bus_isa = 42;

   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);


   memset(mc, 0, sizeof(*mc));



   memcpy(mc->mpc_signature, sig, sizeof(sig));


   mc->mpc_length = sizeof(*mc); /* initially just the header */


   mc->mpc_spec = 0x04;


   mc->mpc_checksum = 0; /* not yet computed */


   memcpy(mc->mpc_oem, oem, sizeof(oem));


   memcpy(mc->mpc_productid, productid, sizeof(productid));


   mc->mpc_oemptr = 0;


   mc->mpc_oemsize = 0;


   mc->mpc_entry_count = 0; /* No entries yet... */


   mc->mpc_lapic = LAPIC_ADDR;


   mc->mpe_length = 0;


   mc->mpe_checksum = 0;


   mc->reserved = 0;



   smp_write_processors(mc);





+/*Bus:		Bus ID	Type*/

smp_write_bus(mc, 0, "PCI   ");
smp_write_bus(mc, 1, "PCI   ");
smp_write_bus(mc, 2, "PCI   ");
smp_write_bus(mc, 3, "PCI   ");
smp_write_bus(mc, 4, "PCI   ");
smp_write_bus(mc, 5, "PCI   ");
smp_write_bus(mc, 6, "PCI   ");
smp_write_bus(mc, bus_isa, "ISA   ");

+/*I/O APICs:	APIC ID	Version	State		Address*/


smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);


smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, VT8237R_APIC_ID, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, VT8237R_APIC_ID, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, VT8237R_APIC_ID, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, VT8237R_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, VT8237R_APIC_ID, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, VT8237R_APIC_ID, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, VT8237R_APIC_ID, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, VT8237R_APIC_ID, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, VT8237R_APIC_ID, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, VT8237R_APIC_ID, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, VT8237R_APIC_ID, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, VT8237R_APIC_ID, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, VT8237R_APIC_ID, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, VT8237R_APIC_ID, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, VT8237R_APIC_ID, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, VT8237R_APIC_ID, 0xf);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);

Very nice. How did you find all the values? Do you have docs or
schematics of the board or did you use some tools?
...



+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/

smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */

/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
return smp_next_mpe_entry(mc);

+}



+unsigned long write_smp_table(unsigned long addr)
+{

void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);

+}
Index: src/mainboard/asus/a8v-e_se/acpi_tables.c
===================================================================
--- src/mainboard/asus/a8v-e_se/acpi_tables.c	(revision 0)
+++ src/mainboard/asus/a8v-e_se/acpi_tables.c	(revision 0)
@@ -0,0 +1,170 @@
+/*


This file is part of the LinuxBIOS project.



written by Stefan Reinauer stepan@openbios.org



ACPI FADT, FACS, and DSDT table support added by



Nick Barker nick.barker9@btinternet.com, and those portions







Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz



Hm, please add
Copyright (C) xxxx Stefan Reinauer stepan@openbios.org
Copyright (C) xxxx Nick Barker nick.barker9@btinternet.com
then. I think this is not done in the original file either, and should
be fixed there, too. Listing all copyright owners explicitly is important.
...






This program is free software; you can redistribute it and/or modify



it under the terms of the GNU General Public License v2 as published by



the Free Software Foundation.







This program is distributed in the hope that it will be useful,



but WITHOUT ANY WARRANTY; without even the implied warranty of



MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the



GNU General Public License for more details.







You should have received a copy of the GNU General Public License



along with this program; if not, write to the Free Software



Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA


*/


+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci_ids.h>



+#include <../../../southbridge/via/vt8237r/vt8237r.h>
+#include <../../../southbridge/via/k8t890/k8t890.h>



+extern unsigned char AmlCode[];
Hm, this is for another patch, but it should be aml_code[] as per
guidelines.
...



+unsigned long acpi_fill_mcfg(unsigned long current)
+{

device_t dev;
struct resource *res;
dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
if (dev) {
res = find_resource(dev, K8T890_MMCONFIG_MBAR);


if (res) {


	current +=


	    acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t


				       *) current,


				      res->base, 0x0, 0x0,


				      0xff);


}


}
return current;

+}
A bit nested. How about this? It eliminates one nesting level and makes
the code a bit more readable and fits more stuff in one line ;-)
unsigned long acpi_fill_mcfg(unsigned long current)
 {
    device_t dev;
    struct resource *res;
dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
    if (!dev)
    	return current;
res = find_resource(dev, K8T890_MMCONFIG_MBAR);
    if (res) {
    	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
    				current, res->base, 0x0, 0x0, 0xff);
    }
return current;
 }
...



+unsigned long acpi_fill_madt(unsigned long current)
+{

unsigned int gsi_base = 0x18;

/* create all subtables for processors */
current = acpi_create_madt_lapics(current);

/* Write SB IOAPIC */
current +=
   acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, VT8237R_APIC_ID,


		    VT8237R_APIC_BASE, 0);



/* Write NB IOAPIC */
current +=
   acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, K8T890_APIC_ID,


		    K8T890_APIC_BASE, gsi_base);


/* IRQ9 ACPI active low */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
				current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);



/* IRQ0 -> APIC IRQ2 */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
				current, 0, 0, 2, 0x0);	



/* create all subtables for processors */
current =
   acpi_create_madt_lapic_nmis(current,


			MP_IRQ_TRIGGER_EDGE |


			MP_IRQ_POLARITY_HIGH, 1);



return current;

+}




+unsigned long write_acpi_tables(unsigned long start)
+{

unsigned long current;
acpi_rsdp_t *rsdp;
acpi_srat_t *srat;
acpi_rsdt_t *rsdt;
acpi_mcfg_t *mcfg;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;

/* Align ACPI tables to 16byte */
start = (start + 0x0f) & -0x10;
current = start;

printk_info("ACPI: Writing ACPI tables at %lx...\n", start);

/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);

/* clear all table memory */
memset((void *) start, 0, current - start);

acpi_write_rsdp(rsdp, rsdt);
acpi_write_rsdt(rsdt);

/*
* We explicitly add these tables later on:


*/


printk_debug("ACPI:     * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);

dsdt = (acpi_header_t *) current;
current += ((acpi_header_t *) AmlCode)->length;
memcpy((void *) dsdt, (void *) AmlCode,
      ((acpi_header_t *) AmlCode)->length);


dsdt->checksum = 0;	// don't trust intel iasl compiler to get this right
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
printk_debug("ACPI:     * DSDT @ %08x Length %x\n", dsdt,
     dsdt->length);


printk_debug("ACPI:     * FADT\n");

fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);

acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdt, fadt);

printk_debug("ACPI:    * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdt, hpet);

/* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI:    * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdt, madt);

printk_debug("ACPI:    * MCFG\n");
mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg);
current += mcfg->header.length;
acpi_add_table(rsdt, mcfg);

/* SRAT */
printk_debug("ACPI:    * SRAT\n");
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current += srat->header.length;
acpi_add_table(rsdt, srat);

printk_info("ACPI: done.\n");
return current;

+}
Index: src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- src/mainboard/asus/a8v-e_se/Options.lb	(revision 0)
+++ src/mainboard/asus/a8v-e_se/Options.lb	(revision 0)
@@ -0,0 +1,313 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License v2 as published by
+## the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##



+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+##uses USE_OPTION_TABLE
+##uses CONFIG_LB_MEM_TOPK



+uses HAVE_ACPI_TABLES



+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HT_FREQ_1G_SUPPORT



+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT



+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID



+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+#bx_b005+
+uses SB_HT_CHAIN_ON_BUS0



+## ROM_SIZE is the size of boot ROM that this board will use.
+#512K bytes
+default ROM_SIZE=512 * 1024



+#1M bytes
+#bx- default ROM_SIZE=1024 * 1024



+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#256K
+default FALLBACK_SIZE=256 * 1024



+###
+### Build options
+###



+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1



+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=0



+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=0
+default IRQ_SLOT_COUNT=11



+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1



+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=0
Make this 1. If the file is there already, why not use it?
...



+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123



+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_PHYSICAL_CPUS=1
+default CONFIG_LOGICAL_CPUS=1



+#acpi
+default HAVE_ACPI_TABLES=1



+#CHIP_NAME ?
+#default CONFIG_CHIP_NAME=1



+#1G memory hole
+#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000



+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1



+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0



+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0



+#make the SB HT chain on bus 0, default is not (0)
+#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2



+##bx_b005+ make the SB HT chain on bus 0
+default SB_HT_CHAIN_ON_BUS0=1



+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0



+#VGA
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1



+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcc000
+default DCACHE_RAM_SIZE=0x4000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0



+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0




+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1



+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="A8V-E SE"
+default MAINBOARD_VENDOR="ASUS"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1043
+#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
Is it really 0x1234? Looks like a dummy value, but I might be wrong.
...



+###
+### LinuxBIOS layout values
+###



+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 64 * 1024



+##
+## Use a small 8K stack
+##
+default STACK_SIZE= 8 * 1024



+##
+## Use a small 256K heap
+##
+default HEAP_SIZE=256 * 1024



+#more 1M for pgtbl
+##default CONFIG_LB_MEM_TOPK=2048



+##
+## Only use the option table in a normal image
+##
+##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE



+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000



+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1



+###
+### Defaults of options that you may want to override in the target config file
+###



+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"



+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0



+##
+## The Serial Console
+##



+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1



+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200



+# Select the serial console base port
+default TTYS0_BASE=0x3f8



+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3



+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details



+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8



+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"



+### End Options.lb
+end
Index: src/mainboard/asus/a8v-e_se/chip.h
===================================================================
--- src/mainboard/asus/a8v-e_se/chip.h	(revision 0)
+++ src/mainboard/asus/a8v-e_se/chip.h	(revision 0)
@@ -0,0 +1,24 @@
+/*


This file is part of the LinuxBIOS project.







Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz







This program is free software; you can redistribute it and/or modify



it under the terms of the GNU General Public License v2 as published by



the Free Software Foundation.







This program is distributed in the hope that it will be useful,



but WITHOUT ANY WARRANTY; without even the implied warranty of



MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the



GNU General Public License for more details.







You should have received a copy of the GNU General Public License



along with this program; if not, write to the Free Software



Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA


*/


+extern struct chip_operations mainboard_via_a8v_ops;
extern struct chip_operations mainboard_asus_a8v_e_se_ops;
...



+struct mainboard_asus_a8v_config {
struct mainboard_asus_a8v_e_se_config
...



+};
Index: src/mainboard/asus/a8v-e_se/dsdt.asl
===================================================================
--- src/mainboard/asus/a8v-e_se/dsdt.asl	(revision 0)
+++ src/mainboard/asus/a8v-e_se/dsdt.asl	(revision 0)
@@ -0,0 +1,241 @@
+/*


This file is part of the LinuxBIOS project.







Minimalist ACPI DSDT table for EPIA-M / MII



(C) Copyright 2004 Nick Barker Nick.Barker9@btinternet.com







(C) Copyright 2007 Rudolf Marek r.marek@assembler.cz







ISA portions taken from QEMU acpi-dsdt.dsl



This program is free software; you can redistribute it and/or modify



it under the terms of the GNU General Public License v2 as published by



the Free Software Foundation.







This program is distributed in the hope that it will be useful,



but WITHOUT ANY WARRANTY; without even the implied warranty of



MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the



GNU General Public License for more details.







You should have received a copy of the GNU General Public License



along with this program; if not, write to the Free Software



Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA


*/



+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{

/*
* Define the main processor


*/


Scope (_PR)
{
Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}


Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}


}

/* For now only define 2 power states:
*  - S0 which is fully on


*  - S5 which is soft off


* any others would involve declaring the wake up methods


*/


Name (_S0, Package () {0x00, 0x00, 0x00, 0x00 })
Name (_S5, Package () {0x02, 0x02, 0x00, 0x00 })

/* Root of the bus hierarchy */
Scope (_SB)
{


/* top PCI device */


Device (PCI0)


{


	Name (_HID, EisaId ("PNP0A03"))


	Name (_ADR, 0x00)


	Name (_UID, 0x00)


	Name (_BBN, 0x00)



	/* PCI Routing Table */


	//aaa


	Name (_PRT, Package () {


                   Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, //slot 0xB


   	            Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },


           	    Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },


                   Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },


   	            Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, //Slot 0xC


           	    Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },


           	    Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },


	    Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },


   	            Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, //Slot 0xD


           	    Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },


           	    Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },


	    Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },


   	            Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, //0xf SATA IRQ 20


           	    Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, //0xf NAtive IDE IRQ 20


   	            Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, //USB routing


           	    Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },


           	    Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },


	    Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },


	    Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, //AC97 MC97


   	            Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, //PCIE16 bridge IRQ27


           	    Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },


           	    Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },


	    Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },


   	            Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, //PCIE bridge IRQ31


           	    Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, //IRQ36


           	    Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, //IRQ39


	    Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } //IRQ43


       		})




Device (PEGG)


{


	Name (_ADR, 0x00020000)


	Name (_UID, 0x00)


	Name (_BBN, 0x02)



	Name (_PRT, Package () {


                   Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, //PCIE IRQ24-IRQ27


   	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },


           	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },


                   Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },


	})	


} //end of PCIEG



Device (PEX0)


{


	Name (_ADR, 0x00030000)


	Name (_UID, 0x00)


	Name (_BBN, 0x03)



	Name (_PRT, Package () {


                   Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, //PCIE IRQ28-IRQ31


   	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },


           	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },


                   Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },


	})	


} //end of PEX0



Device (PEX1)


{


	Name (_ADR, 0x00030001)


	Name (_UID, 0x00)


	Name (_BBN, 0x04)



	Name (_PRT, Package () {


                   Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, //PCIE IRQ32-IRQ35


   	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },


           	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },


                   Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },


	})	


} //end f PEX1



Device (PEX2)


{


	Name (_ADR, 0x00030002)


	Name (_UID, 0x00)


	Name (_BBN, 0x05)



	Name (_PRT, Package () {


                   Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, //PCIE IRQ36-IRQ39


   	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },


           	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },


                   Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },


	})	


} //end f PEX2



Device (PEX3)


{


	Name (_ADR, 0x00030003)


	Name (_UID, 0x00)


	Name (_BBN, 0x06)



	Name (_PRT, Package () {


                   Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, //PCIE IRQ40-IRQ43


   	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },


           	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },


                   Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },


	})	


} //end f PEX3



   Device (ISA) {


       Name (_ADR, 0x00110000)



       /* Keyboard seems to be important for WinXP install */


       Device (KBD)


       {


           Name (_HID, EisaId ("PNP0303"))


           Method (_STA, 0, NotSerialized)


           {


               Return (0x0f)


           }



           Method (_CRS, 0, NotSerialized)


           {


                Name (TMP, ResourceTemplate ()


                {


               IO (Decode16,


                   0x0060,             // Address Range Minimum


                   0x0060,             // Address Range Maximum


                   0x01,               // Address Alignment


                   0x01,               // Address Length


                   )


               IO (Decode16,


                   0x0064,             // Address Range Minimum


                   0x0064,             // Address Range Maximum


                   0x01,               // Address Alignment


                   0x01,               // Address Length


                   )


               IRQNoFlags ()


                   {1}


               })


               Return (TMP)


           }


       }



   /* PS/2 mouse */


       Device (MOU) 


       {


           Name (_HID, EisaId ("PNP0F13"))


           Method (_STA, 0, NotSerialized)


           {


               Return (0x0f)


           }



           Method (_CRS, 0, NotSerialized)


           {


               Name (TMP, ResourceTemplate ()


               {


                    IRQNoFlags () {12}


               })


               Return (TMP)


           }


       }



   /* PS/2 floppy controller */


   Device (FDC0)


   {


       Name (_HID, EisaId ("PNP0700"))


Method (_STA, 0, NotSerialized)


{


    Return (0x0F)


}


Method (_CRS, 0, NotSerialized)


{


    Name (BUF0, ResourceTemplate ()


               {


                   IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)


                   IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)


                   IRQNoFlags () {6}


                   DMA (Compatibility, NotBusMaster, Transfer8) {2}


               })


    Return (BUF0)


}


   } //FD END



   } //ISA END



} // End of PCI0


} // End of _SB


+} // End of Definition Block



Index: src/mainboard/asus/a8v-e_se/mainboard.c
--- src/mainboard/asus/a8v-e_se/mainboard.c	(revision 0)
+++ src/mainboard/asus/a8v-e_se/mainboard.c	(revision 0)
@@ -0,0 +1,31 @@
+/*


This file is part of the LinuxBIOS project.







Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz







This program is free software; you can redistribute it and/or modify



it under the terms of the GNU General Public License v2 as published by



the Free Software Foundation.







This program is distributed in the hope that it will be useful,



but WITHOUT ANY WARRANTY; without even the implied warranty of



MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the



GNU General Public License for more details.







You should have received a copy of the GNU General Public License



along with this program; if not, write to the Free Software



Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA


*/


+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"



+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_asus_a8v_ops = {
struct chip_operations mainboard_asus_a8v_e_se_ops
...

CHIP_NAME("A8V Mainboard")

CHIP_NAME("ASUS A8V-E SE Mainboard")
...
+};
+#endif
Index: src/mainboard/asus/a8v-e_se/cmos.layout
===================================================================
--- src/mainboard/asus/a8v-e_se/cmos.layout	(revision 0)
+++ src/mainboard/asus/a8v-e_se/cmos.layout	(revision 0)
@@ -0,0 +1,98 @@
+entries



+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory





+enumerations



+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%



+checksums



+checksum 392 983 984




Index: src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
--- src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	(revision 0)
+++ src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	(revision 0)
@@ -0,0 +1,344 @@
+/*


This file is part of the LinuxBIOS project.







...


Based on other cache_as_ram_auto.c.



Drop this line, not needed.
...


Copyright (C) 2006 AMD



Written by Yinghai Lu yinghailu@amd.com for AMD.



Copyright (C) 2006 MSI



Written by Bingxun Shi bingxunshi@gmail.com for MSI.







Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz







This program is free software; you can redistribute it and/or modify



it under the terms of the GNU General Public License as published by



the Free Software Foundation; either version 2 of the License, or



(at your option) any later version.







This program is distributed in the hope that it will be useful,



but WITHOUT ANY WARRANTY; without even the implied warranty of



MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the



GNU General Public License for more details.







You should have received a copy of the GNU General Public License



along with this program; if not, write to the Free Software



Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA


*/


+#define ASSEMBLY 1
+#define __ROMCC__



+#define RAMINIT_SYSINFO 1



+#define CACHE_AS_RAM_ADDRESS_DEBUG 0



+unsigned int get_sbdn(unsigned bus);



+//used by raminit
+#define QRANK_DIMM_SUPPORT 1



+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 1
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1



+//#define DEBUG_SMBUS 1



+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"



+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"



+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"



+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif



+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "northbridge/amd/amdk8/early_ht.c"




+#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"



+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"



+#include "northbridge/amd/amdk8/setup_resource_map.c"



+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
+#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)





...
+//#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
Drop?
...
+static void memreset_setup(void)
+{
+}



+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}




+static inline int spd_read_byte(unsigned device, unsigned address)
+{

return smbus_read_byte(device, address);

+}



+#define K8_4RANK_DIMM_SUPPORT 1



+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "sdram/generic_sdram.c"



+#include "cpu/amd/dualcore/dualcore.c"



+#include "southbridge/via/k8t890/k8t890_early_car.c"



+#include "cpu/amd/car/copy_and_run.c"



+#include "cpu/amd/car/post_cache_as_ram.c"



+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"



+#include "northbridge/amd/amdk8/resourcemap.c"




+void activate_spd_rom(const struct mem_controller *ctrl)
+{



+}



+void hard_reset(void)
+{

/* nothing to do */

Drop the comment, it's incorrect.
...

print_info("NO HARD RESET  FIX ME!\n");

+}



+void soft_reset(void)
+{

uint8_t tmp;
set_bios_reset();
print_debug("soft reset \r\n");

/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
tmp |= 0x01;
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);

Is this tested for this board or a copy from somewhere else?
...


while (1) {
/* daisy daisy ... */



???
...

hlt();


}

+}



+unsigned int get_sbdn(unsigned bus)
+{

device_t dev;

/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.


*/



Comment is incorrect, clone from somewhere else.
...

dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, 0x3227),

What's 0x3227? Use the respective ID from pci_ids.h, please.
...

		       bus);


return (dev >> 15) & 0x1f;


+}



+#if USE_FALLBACK_IMAGE == 1




+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+//        unsigned last_boot_normal_x = last_boot_normal();
+//FIXME


unsigned last_boot_normal_x = 1;

+//         print_info("failover process\r\n");


u8 reg;

pnp_enter_ext_func_mode(SERIAL_DEV);
reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));	/* we have 24MHz input */

reg = pnp_read_config(SERIAL_DEV, 0x2A);
pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1));	/* we have GPIO for KB/MS PIN */

reg = pnp_read_config(SERIAL_DEV, 0x2C);
pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0));	/* we have all RESTOUT and even some reserved bits too */

pnp_exit_ext_func_mode(SERIAL_DEV);

pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
pnp_write_config(GPIO_DEV, 0xe0, 0xde);	// 1101110  0=output 1=input
pnp_write_config(GPIO_DEV, 0xe1, 0x1);	//set output val
pnp_write_config(GPIO_DEV, 0xe2, 0x0);	//no inversion
pnp_write_config(GPIO_DEV, 0xe3, 0x3);	//0000 0011 0=output 1=input
pnp_write_config(GPIO_DEV, 0xe4, 0xa4);	//set output val
pnp_write_config(GPIO_DEV, 0xe5, 0x0);	//no inversion
pnp_write_config(GPIO_DEV, 0x30, 0x9);	//Enable GPIO 2 & GPIO 5
pnp_exit_ext_func_mode(GPIO_DEV);


w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();

print_info("now booting... fallback\r\n");

/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {


	goto normal_image;


} else {


	goto fallback_image;


}


}

/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */

enumerate_ht_chain();

/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;


}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;


} else {
goto fallback_image;


}
 normal_image:


//print_info("JMP normal image\r\n");

__asm__ volatile ("jmp __normal_image":	/* outputs */
	  :"a" (bist), "b"(cpu_init_detectedx)	/* inputs */


   );



 fallback_image:


;

+}
+#endif



+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);



+void cache_as_ram_main(unsigned long bist,

       unsigned long cpu_init_detectedx)



+{



+#if USE_FALLBACK_IMAGE == 1

failover_process(bist, cpu_init_detectedx);

+#endif

real_main(bist, cpu_init_detectedx);


+}




+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{

static const uint16_t spd_addr[] = {
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,


(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,



+#if CONFIG_MAX_PHYSICAL_CPUS > 1

(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,


(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,



+#endif

};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
   (DCACHE_RAM_BASE + DCACHE_RAM_SIZE -


    DCACHE_RAM_GLOBAL_VAR_SIZE);


char *p;
u8 reg;

pnp_enter_ext_func_mode(SERIAL_DEV);
reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));	/* we have 24MHz input */

reg = pnp_read_config(SERIAL_DEV, 0x2A);
pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1));	/* we have GPIO for KB/MS PIN */

reg = pnp_read_config(SERIAL_DEV, 0x2C);
pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0));	/* we have all RESTOUT and even some reserved bits too */

pnp_exit_ext_func_mode(SERIAL_DEV);

pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
pnp_write_config(GPIO_DEV, 0xe0, 0xde);	// 1101110  0=output 1=input
pnp_write_config(GPIO_DEV, 0xe1, 0x1);	//set output val
pnp_write_config(GPIO_DEV, 0xe2, 0x0);	//no inversion
pnp_write_config(GPIO_DEV, 0xe3, 0x3);	//0000 0011 0=output 1=input
pnp_write_config(GPIO_DEV, 0xe4, 0xa4);	//set output val
//0x10 seems to control something with SGD VIA

pnp_write_config(GPIO_DEV, 0xe5, 0x0);	//no inversion
pnp_write_config(GPIO_DEV, 0x30, 0x9);	//Enable GPIO 2 & GPIO 5
pnp_exit_ext_func_mode(GPIO_DEV);


w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();

print_info("now booting... real_main\r\n");

if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);


}
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_default_resource_map();
setup_coherent_ht_domain();
wait_all_core0_started();
print_info("now booting... Core0 started\r\n");


+#if CONFIG_LOGICAL_CPUS==1

// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);

+#endif

init_timer();
ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);

/* Fixme it assumes that 1000MHz LDT is selected. */
needs_reset |= k8t890_early_setup_car(16, 0x6);

if (needs_reset) {
print_debug("ht reset -\r\n");


soft_reset();


}
/* stop the APs so we can start them later in init */
   allow_all_aps_stop(bsp_apicid);


/* It's the time to set ctrl now; */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();

+}



Index: targets/asus/a8v-e_se/Config.lb
--- targets/asus/a8v-e_se/Config.lb	(revision 0)
+++ targets/asus/a8v-e_se/Config.lb	(revision 0)
@@ -0,0 +1,102 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License v2 as published by
+## the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##



+target a8v-e_se
+mainboard asus/a8v-e_se



+romimage "normal"
+#       48K for SCSI FW
+#        option ROM_SIZE = 475136
+#       option ROM_SIZE = 512*1024-36*1024

 option ROM_SIZE = 512*1024



+#       48K for SCSI FW and 48K for ATI ROM
+#       option ROM_SIZE = 425984
+#       64K for Etherboot
+#        option ROM_SIZE = 458752
+#        option USE_FAILOVER_IMAGE=0

option USE_FALLBACK_IMAGE=0


+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x18800

  option ROM_IMAGE_SIZE=0x20000



+#      option ROM_IMAGE_SIZE=0x15800

  option XIP_ROM_SIZE=0x40000


  option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"



+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#      payload ../../../payloads/tg3.zelf
+#      payload ../../../../payloads/tg3_vga.zelf

 payload filo.elf



+#       payload /tg3--filo.elf
+#      payload /payload
+#      payload ../../../../payloads/e1000_vga.zelf
+#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#      payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end



+romimage "fallback"

  option USE_FALLBACK_IMAGE=1


#       option USE_FAILOVER_IMAGE=0


+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x19800

  option ROM_IMAGE_SIZE=0x20000



+#      option ROM_IMAGE_SIZE=0x15800

  option XIP_ROM_SIZE=0x40000


  option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"



+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#      payload ../../../payloads/tg3.zelf
+#      payload ../../../../payloads/tg3_vga.zelf
+#      payload ../../../../payloads/memtest
+#      payload ../../../../payloads/e1000_vga.zelf
+#      payload ../../../../payloads/filo_hda.zelf

 payload filo.elf



+#       payload /tg3--filo.elf
+#      payload /payload
+#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#      payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
Please drop all commented payload lines, they're not needed.
Looks nice otherwise.
Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

    

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Re: [LinuxBIOS] [PATCH] Add support for the Asus A8V-E SE motherboard

Index: src/mainboard/asus/a8v-e_se/fadt.c

Index: src/mainboard/asus/a8v-e_se/mainboard.c

Index: src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c

Index: targets/asus/a8v-e_se/Config.lb