Maybe it make sense to review that in the google docs? Since its quite a bit of documentation it would probably be easier to review and/or edit it in google docs until publishing on gerrit. We can of course also review it afterwards in gerrit but for the big part its probably easier to do it in google docs via comments and stuff. Just a thought though.
Max
Am Do., 20. Apr. 2023 um 19:59 Uhr schrieb Martin Roth via coreboot < coreboot@coreboot.org>:
Here's some devicetree documentation I started working on, but never published.
https://docs.google.com/document/d/1_pEbupbU9K638uvN1qVNvweP5dP4KuunHWq1NBfC...
Sorry for the google docs link. I'll see what still needs to be done and push it to documentation folder.
Martin
Apr 17, 2023, 02:29 by michal.zygowski@3mdeb.com:
Dear Sir or Madam,
On 11.04.2023 04:41, Chiang.Gain 江有舜 TAO wrote:
Dear Sir
This is Inventec BIOS team, we are trying to port Coreboot to our
Server Board
which is based on Intel CRB ArcherCity.
We have to add “Devicetree.cb” files under mainboard folder, right ?
That's correct.
We had read the following files but we are still confused and don’t
know how to
modify those files to match our design.
Documentation/getting_started/devicetree.md
Documentation/drivers/dt_entries.md
We would like to know if there are any training materials or further
Docs;
particular to “syntax”.
that we can refer to.
AFAIK there is no training for devicetree in particular. The links above
are
already quite detailed and I doubt there are better materials than those
as of
today. I advise to base your devicetree on archercity crb:
https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/archerc...
In short how it works:
For Sapphire Rapids platform the final devicetree is a merge of
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/xeon_sp/spr/c...
and the mainboard's devicetree (the one you trying to create).
As the chipset.cb defines all the default devices all you need to do in mainboard's devicetree is to define the board-specific configuration.
Each
devicetree starts with a chip declaration which has to point to a
directory in
coreboot source that contains a chip.h file. This chips declaration must
be a
soc directory, in your case "chip soc/intel/xeon_sp/spr". Each
declaration must
be closed with an "end" word. Inside the scope of the chip you may place
the
same declarations as in chipset.cb, but set it to your desired values.
E.g. if
your design does not use PCIe root port 12 and 13, you can define the
following:
chip soc/intel/xeon_sp/spr device domain 0 on device pci 1a.0 off end # Intel device 1bb4: PCH PCIe Root Port #12 device pci 1b.0 off end # Intel device 1bb5: PCH PCIe Root Port #13 end end
What is important is to keep the scopes intact. One may disable the
device by
changing "on" to "off". if you would like to override the soc-specific configuration, then you need to look at
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/xeon_sp/spr/c...
The entries in devicetree starting with "register" declaration means you
want to
set a variable defined in chip.h for given chip/soc. And for example if
you
would like to configure a board specific TCC activation offset (aka CPU throttling thermal threshold), you would need to add the following:
chip soc/intel/xeon_sp/spr
register "tcc_offset" = "10"
device domain 0 on device pci 1a.0 off end # Intel device 1bb4: PCH PCIe Root Port #12 device pci 1b.0 off end # Intel device 1bb5: PCH PCIe Root Port #13 end end
The offset is relative to TJmax and the threshold would be TJmax -
tcc_offset.
I could write a whole essay what you can do with devicetree. It is hard
to
explain all possibilities in one mail, it would be great if you could be
more
specific about the problems you have, given that you haven't given any
info
about your hardware. The devicetree contents are specific to given board
design
and they may even require implementing new drivers which have to be
referenced
in the devicetree. Also it may be worth considering coreboot consulting services: https://www.coreboot.org/consulting.html This page: https://doc.coreboot.org/distributions.html should also give you an overview who is doing coreboot work and ships
coreboot
on their devices.
Any kind of helps are appreciated.
Thanks
Gain
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