[coreboot] [PATCH] workaround v2 VIA ROMCC breakage

[Carl-Daniel Hailfinger]

Workaround v2 VIA ROMCC breakage.

Someone please tell me why the network adapter has to be handled by
romcc compiled code.

Signed-off-by: Carl-Daniel Hailfinger

Index: LinuxBIOSv2-tmp2/src/southbridge/via/vt8237r/vt8237r.h
===================================================================
--- LinuxBIOSv2-tmp2/src/southbridge/via/vt8237r/vt8237r.h	(Revision 3660)
+++ LinuxBIOSv2-tmp2/src/southbridge/via/vt8237r/vt8237r.h	(Arbeitskopie)
@@ -29,7 +29,11 @@
 #define VT8237R_SMBUS_IO_BASE		0x400
 /* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */
 #define VT8237R_ACPI_IRQ		0x9
+#if defined(__GNUC__)
 #define VT8237S_SPI_MEM_BASE		0xfed02000ULL
+#else
+#define VT8237S_SPI_MEM_BASE		0xfed02000UL
+#endif
 #define VT8237R_HPET_ADDR		0xfed00000ULL
 #define VT8237R_APIC_BASE		0xfec00000ULL

Index: LinuxBIOSv2-tmp2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- LinuxBIOSv2-tmp2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(Revision 3660)
+++ LinuxBIOSv2-tmp2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(Arbeitskopie)
@@ -354,9 +354,11 @@
    pci_write_config32(dev, 0xbc,
    		   (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));

+#if 0
    /* Set SPI clock to 33MHz. */
    spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
    (*spireg) &= 0xff00;
+#endif
 }

/*
@@ -413,6 +415,7 @@
    if (status == 3)
    	return 0;

+#if 0
    if (rom == NULL) {
    	print_err("No config data specified, using default MAC!\n");
    	n.mac_address[0] = 0x0;
@@ -443,6 +446,7 @@
    	n.checksum = 0x0;
    	rom = &n;
    }
+#endif

rom_write = (u16 *) rom;
    checksum = 0;