The code: /** * Delay Control Settings table from AMD (MCP 0x4C00000F). */ static const struct delay_controls { u8 dimms; u8 devices; u32 slow_hi; u32 slow_low; u32 fast_hi; u32 fast_low; } delay_control_table[] = { /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, };
/* * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM * in slot 0, but it should be clear for all 2 DIMM settings and if a * single DIMM is in slot 1. Bits 54:52 should always be set to '111'. * * Settings for single DIMM and no VTT termination (like DB800 platform) * 0xF2F100FF 0x56960004 * ------------------------------------- * ADDR/CTL have 22 ohm series R * DQ/DQM/DQS have 33 ohm series R */
static void set_delay_control(u8 dimm0, u8 dimm1)
There's no support here for a non-terminated bus! Just that one comment.
Also: * Settings for single DIMM and no VTT termination (like DB800 platform) * 0xF2F100FF 0x56960004
Does this mean 1 DIMM, any number of devs? This is not clear.
A change: static void set_delay_control(u8 dimm0, u8 dimm1, int terminated)
terminated is 0 if there is no termination. Then set 4c00000f accordingly?
ron