[coreboot] [commit] r5615 - in trunk/src: cpu/amd/car cpu/amd/model_lx cpu/via/car mainboard/digitallogic/msm586seg

[repository service]

Author: stepan
Date: Mon Jun  7 10:29:36 2010
New Revision: 5615
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5615

Log:
replace outb -> port 0x80 with post_code() in some places.
Especially most _smbus functions misuse port 0x80 writes for delays.
Signed-off-by: Stefan Reinauer 
Acked-by: Stefan Reinauer

Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc
   trunk/src/cpu/amd/model_lx/cache_as_ram.inc
   trunk/src/cpu/via/car/cache_as_ram.inc
   trunk/src/mainboard/digitallogic/msm586seg/romstage.c

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Sat Jun  5 12:03:08 2010	(r5614)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Mon Jun  7 10:29:36 2010	(r5615)
@@ -49,9 +49,7 @@
    /*for normal part %ebx already contain cpu_init_detected from fallback call */

cache_as_ram_setup:
-
-	movb	$0xA0, %al
-	outb	%al, $0x80
+	post_code(0xa0)

/* enable SSE */
    movl %cr4, %eax
@@ -284,8 +282,7 @@
    orl	$(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
    wrmsr

-	movb	$0xA1, %al
-	outb	%al, $0x80
+	post_code(0xa1)

/* enable cache */
    movl	%cr0, %eax
@@ -301,8 +298,7 @@
    jnc	CAR_FAM10_ap
 fam10_end_part1:

-	movb	$0xA2, %al
-	outb	%al, $0x80
+	post_code(0xa2)

/* Read the range with lodsl*/
    cld
@@ -320,8 +316,7 @@
    movl	$(CacheBase + CacheSize - GlobalVarSize), %eax
    movl	%eax, %esp

-	movb	$0xA3, %al
-	outb	%al, $0x80
+	post_code(0xa3)

jmp	CAR_FAM10_ap_out
 CAR_FAM10_ap:
@@ -363,13 +358,11 @@
    /* retrive init detected */
    movl	%esi, %ebx

-	movb	$0xA4, %al
-	outb	%al, $0x80
+	post_code(0xa4)

CAR_FAM10_ap_out:

-	movb	$0xA5, %al
-	outb	%al, $0x80
+	post_code(0xa5)

/* disable SSE */
    movl %cr4, %eax
@@ -386,8 +379,7 @@
    call	cache_as_ram_main
    /* We will not go back */

-	movb	$0xAF, %al	/* Should never see this postcode */
-	outb	%al, $0x80
+	post_code(0xaf)		/* Should never see this postcode */

fixed_mtrr_msr:
    .long	0x250, 0x258, 0x259

Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/model_lx/cache_as_ram.inc	Sat Jun  5 12:03:08 2010	(r5614)
+++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc	Mon Jun  7 10:29:36 2010	(r5615)
@@ -169,8 +169,8 @@
    popl	%ecx
    cmpl	%ecx, %edx
    je	DCacheSetupGood
-	movb	$0xC5, %al
-	outb	%al, $0x80
+
+	post_code(0xc5)
 DCacheSetupBad:
    hlt		/* issues */
    jmp DCacheSetupBad

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Sat Jun  5 12:03:08 2010	(r5614)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Mon Jun  7 10:29:36 2010	(r5615)
@@ -152,8 +152,8 @@
    movl	%eax, %esp

#ifdef CARTEST
-testok:	movb $0x40,%al
-	outb %al, $0x80
+testok:	
+	post_code(0x40)
    xorl	%edx, %edx
    xorl	%eax, %eax
    movl	$0x5c5c,%edx

Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Sat Jun  5 12:03:08 2010	(r5614)
+++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Mon Jun  7 10:29:36 2010	(r5615)
@@ -183,7 +183,7 @@

//			while(1)
    print_err("STATIC MEM DONE\n");
-	outb(0xee, 0x80);
+	post_code(0xee);
    print_err("loop forever ...\n");

#if 0
@@ -231,13 +231,14 @@
        *dst = *src;
        //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
        dst++, src++;
-	    outb((unsigned char)i, 0x80);
+	    post_code(i & 0xff);
      }
    }
    dumpmem();
-	outb(0, 0x80);
+	post_code(0x00);
+
    print_err("loop forever\n");
-	outb(0xdd, 0x80);
+	post_code(0xdd);
         __asm__ volatile(
    		 "movl %0, %%edi\n\t"
    		 "jmp *%%edi\n\t"