It looks like grub returns from execution. Probably because it's unhappy about something ..
Were you able to use the same payload, say, in qemu?
On Apr 5, 2013, at 16:42, Paul Menzel paulepanter@users.sourceforge.net wrote:
Dear coreboot folks,
on the ASRock E350M1 I build coreboot (hash 44af3db) with the VGA ROM and GRUB as payload.
$ build/cbfstool build/coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 alignment: 64 bytes Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 1776 pci1002,9802.rom 0x740 optionrom 65536 fallback/romstage 0x10780 stage 347052 fallback/coreboot_ram 0x65380 stage 205897 fallback/payload 0x97840 payload 195518 (empty) 0xc7440 null 337698And now it fails and I only updated the coreboot code revision.
[…] SMBIOS tables: 275 bytes. Adding CBMEM entry as no. 6 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 57df Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0xc7fee000 rom_table_end = 0xc7fee000 ... aligned to 0xc7ff0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000c7fdffff: RAM 3. 00000000c7fe0000-00000000c7ffffff: CONFIGURATION TABLES 4. 00000000c8000000-00000000dfffffff: RESERVED 5. 00000000f8000000-00000000f8ffffff: RESERVED 6. 0000000100000000-000000021effffff: RAM Wrote coreboot table at: c7fee000, 0x200 bytes, checksum c1b6 coreboot table: 536 bytes. Multiboot Information structure has been written. FREE SPACE 0. c7ff6000 0000a000 GDT 1. c7fe0200 00000200 IRQ TABLE 2. c7fe0400 00001000 SMP TABLE 3. c7fe1400 00001000 ACPI 4. c7fe2400 0000b400 SMBIOS 5. c7fed800 00000800 COREBOOT 6. c7fee000 00008000 CBFS: Looking for 'fallback/payload' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: (unmatched file @0x740: pci1002,9802.rom) CBFS: (unmatched file @0x10780: fallback/romstage) CBFS: (unmatched file @0x65380: fallback/coreboot_ram) CBFS: Found file (offset=0x97878, len=195518). Loading segment from rom address 0xffc97878 code (compression=1) New segment dstaddr 0x8200 memsize 0xe504 srcaddr 0xffc978cc filesize 0x417d (cleaned up) New segment addr 0x8200 size 0xe504 offset 0xffc978cc filesize 0x417d Loading segment from rom address 0xffc97894 code (compression=1) New segment dstaddr 0x100000 memsize 0x85b64 srcaddr 0xffc9ba49 filesize 0x2b9ed (cleaned up) New segment addr 0x100000 size 0x85b64 offset 0xffc9ba49 filesize 0x2b9ed Loading segment from rom address 0xffc978b0 Entry Point 0x00008200 Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d lb: [0x0000000000200000, 0x0000000000370038) Post relocation: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d using LZMA [ 0x00008200, 0000f14f, 0x00016704) <- ffc978cc Clearing Segment: addr: 0x000000000000f14f memsz: 0x00000000000075b5 dest 00008200, end 00016704, bouncebuffer c7cfff90 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed lb: [0x0000000000200000, 0x0000000000370038) Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed using LZMA Boot failedUnfortunately I do not understand what is happening above. Could you give me a hint, what went wrong, please?
Thanks,
Paul
coreboot-4.0-3980-g44af3db Fri Apr 5 14:04:48 CEST 2013 starting... BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 agesawrapper_amdinitmmio passed. agesawrapper_amdinitreset passed. agesawrapper_amdinitearly BSP Family_Model: 00500f10 cpu_init_detectedx = 00000001 agesawrapper_amdinitmmio passed. agesawrapper_amdinitreset passed. agesawrapper_amdinitearly passed. agesawrapper_amdinitpost passed. agesawrapper_amdinitenv passed. Loading image. CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: (unmatched file @0x740: pci1002,9802.rom) CBFS: (unmatched file @0x10780: fallback/romstage) CBFS: Found file (offset=0x653b8, len=205897). CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1507384 bytes), entry @ 0x200000 Jumping to image. coreboot-4.0-3980-g44af3db Fri Apr 5 14:04:48 CEST 2013 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 Mainboard E350M1 Enable. scan_static_bus for Root Device setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000002 setup_uma_memory: uma size 0x18000000, memory start 0xc8000000 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... AP siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1022/1510] ops PCI: 00:00.0 [1022/1510] enabled PCI: 00:01.0 [1002/9802] enabled PCI: 00:01.1 [1002/1314] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. sb800_enable() SB800 - Smbus.c - alink_ab_indx - Start. SB800 - Smbus.c - alink_ab_indx - End. PCI: 00:11.0 [1002/4390] enabled sb800_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb800_enable() sm_init(). IOAPIC: Clearing IOAPIC at 0xfec00000 IOAPIC: 24 interrupts IOAPIC: reg 0x00000000 value 0x00000000 0x00010000 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb800_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb800_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb800_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled sb800_enable() Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:15.0 subordinate bus PCI Express PCI: 00:15.0 [1002/43a0] enabled sb800_enable() PCI: 00:16.0 [1002/4397] ops PCI: 00:16.0 [1002/4397] disabled sb800_enable() SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. PCI: 00:18.0 [1022/1700] enabled PCI: 00:18.1 [1022/1701] enabled PCI: 00:18.2 [1022/1702] enabled PCI: 00:18.3 [1022/1703] enabled PCI: 00:18.4 [1022/1704] enabled PCI: 00:18.5 [1022/1718] enabled PCI: 00:18.6 [1022/1716] enabled PCI: 00:18.7 [1022/1719] enabled PCI: Left over static devices: PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: Check your devicetree.cb. scan_static_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a enabled PNP: 002e.b enabled scan_static_bus for PCI: 00:14.3 done do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:15.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 PCI: pci_scan_bus returning with max=002 scan_static_bus for Root Device done done found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Fam14h - domain_read_resources DOMAIN: 0000 read_resources bus 0 link: 0
Fam14h - nb_read_resources PCI: 00:14.0 read_resources bus 0 link: 0 I2C: 00:50 missing read_resources I2C: 00:51 missing read_resources PCI: 00:14.0 read_resources bus 0 link: 0 done SB800 - Lpc.c - lpc_read_resources - Start. SB800 - Lpc.c - lpc_read_resources - End. PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:14.4 read_resources bus 1 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 done PCI: 00:15.0 register 10(ffffffff), read-only ignoring it PCI: 00:15.0 register 14(ffffffff), read-only ignoring it PCI: 00:15.0 register 38(ffffffff), read-only ignoring it PCI: 00:15.0 read_resources bus 2 link: 0 PCI: 00:15.0 read_resources bus 2 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC
<.config>
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