Re: [coreboot] [PATCH] Table code cleanup

[Bao, Zheng]

Please see the output below.

Zheng

-----------output with HAVE_HIGH_TABLES ------------------
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Wrote the mp table end at: 000f0410 - 000f0524
High Tables Base is 7fff0000.
Writing IRQ routing tables to 0x7fff0000...write_pirq_routing_table
done.
Wrote the mp table end at: 7fff0410 - 7fff0524
ACPI: Writing ACPI tables at 7fff0800...
ACPI:    * HPET
ACPI: added table 1/9 Length now 40
ACPI:    * MADT
ACPI: added table 2/9 Length now 44
ACPI:    * SSDT
processor_brand=AMD Athlon(tm) 64 X2 Dual Core Processor 3400+
Pstates Algorithm ...
Pstate_freq[0] = 1800MHz        Pstate_vid[0] = 18      Pstate_volt[0] =
1100mv Pstate_power[0]
 = 35000mw
Pstate_freq[1] = 1000MHz        Pstate_vid[1] = 22      Pstate_volt[1] =
1000mv Pstate_power[1]
 = 16069mw
ACPI: added table 3/9 Length now 48
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * DSDT @ 7fff0bee Length 27c8
ACPI:    * FADT
pm_base: 0x0800
ACPI: added table 4/9 Length now 52
ACPI: done.
Moving GDT to 0x500...ok
Multiboot Information structure has been written.
Writing high table forward entry at 0x00000800
Wrote coreboot table at: 00000800 - 00000818  checksum 470f
New low_table_end: 0x00000818
Now going to write high coreboot table at 0x7fff38d0
rom_table_end = 0x7fff38d0
Adjust low_table_end from 0x00000818 to 0x00001000
Adjust rom_table_end from 0x7fff38d0 to 0x80000000
Adding high table area
uma_memory_start=0x78000000, uma_memory_size=0x0
Wrote coreboot table at: 7fff38d0 - 7fff3ac8  checksum 4b5b

elfboot: Attempting to load payload.
rom_stream: 0xfffc0000 - 0xfffdffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
--------------end of output with HAVE_HIGH_TABLES-----------------

-------------- output without HAVE_HIGH_TABLES ---------------------
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Wrote the mp table end at: 000f0410 - 000f0524
ACPI: Writing ACPI tables at f0800...
ACPI:    * HPET
ACPI: added table 1/9 Length now 40
ACPI:    * MADT
ACPI: added table 2/9 Length now 44
ACPI:    * SSDT
processor_brand=AMD Athlon(tm) 64 X2 Dual Core Processor 3400+
Pstates Algorithm ...
Pstate_freq[0] = 1800MHz        Pstate_vid[0] = 18      Pstate_volt[0] =
1100mv Pstate_power[0]
 = 35000mw
Pstate_freq[1] = 1000MHz        Pstate_vid[1] = 22      Pstate_volt[1] =
1000mv Pstate_power[1]
 = 16069mw
ACPI: added table 3/9 Length now 48
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * DSDT @ 000f0bee Length 27c8
ACPI:    * FADT
pm_base: 0x0800
ACPI: added table 4/9 Length now 52
ACPI: done.
Moving GDT to 0x500...ok
Multiboot Information structure has been written.
Adjust low_table_end from 0x00000800 to 0x00001000
Adjust rom_table_end from 0x000f38d0 to 0x00100000
uma_memory_start=0x78000000, uma_memory_size=0x0
Wrote coreboot table at: 00000800 - 00000a20  checksum 4307
--------------end of output without HAVE_HIGH_TABLES ------------

-----Original Message-----
From: Myles Watson [mailto:[e-mail]] 
Sent: Friday, May 15, 2009 11:08 AM
To: Bao, Zheng; 'Patrick Georgi'
Cc: 'coreboot'
Subject: RE: [coreboot] [PATCH] Table code cleanup
> It still failed on dbm690t + filo.
>
> Do I have to patch the high_low.diff?

No.  Just that patch.

Could you send the output?  With and without HAVE_HIGH_TABLES would be
nice.

Thanks,
Myles