* Stefan Reinauer stefan.reinauer@coreboot.org [110119 07:37]:
- Peter Stuge peter@stuge.se [110117 03:25]:
repository service wrote:
+++ trunk/src/pc80/mc146818rtc_early.c Fri Jan 14 08:40:24 2011 (r6253)
..
static inline int do_normal_boot(void) {
char *cmos_default = cbfs_find_file("cmos.default", 0xaa); unsigned char byte;
int i;
if (cmos_error() || !cmos_chksum_valid()) {
if (cmos_default) {printk_warning("WARNING - CMOS CORRUPTED. RESTORING DEFAULTS.\n");/* First 14 bytes are reserved forRTC and ignored by nvramtool, too.Only 128 bytes: 128+ requires cmos configuration andcontains only suspend-to-ram data, which isn't partof the recovery procedure. */for (i = 14; i < 128; i++) {cmos_write(cmos_default[i], i);}/* Now reboot to run with default cmos. */outb(0x06, 0xcf9);for (;;) asm("hlt"); /* Wait for reset! */Isn't this kinda ugly to have in the rtc code? We could at least have some kind of reset/reboot function..
agreed. Is this possible? Maybe romcc makes it harder ...
To update on this, there are many different ways to do a reset. The above is not among those implemented by (m)any mainboards I think. So to keep this reliable because it was tested, I suggest we leave it for now. It would be nice to see someone cleanup all the different reset methods, but this is not going to be a fun job. It's highly likely that we actually use the "wrong" reset in many places.
./pc80/mc146818rtc_early.c: outb(0x06, 0xcf9); ./northbridge/intel/i945/raminit.c: outb(0x00, 0xcf9); ./northbridge/intel/i945/raminit.c: outb(0x0e, 0xcf9); ./northbridge/intel/i945/raminit.c: outb(0x00, 0xcf9); ./northbridge/intel/i945/raminit.c: outb(0x0e, 0xcf9); ./northbridge/intel/i945/early_init.c: outb(0x06, 0xcf9); ./northbridge/via/cx700/reset.c: outb((1 << 2) | (1 << 1), 0xcf9); ./northbridge/via/vx800/examples/romstage.c: outb(6, 0xcf9); ./southbridge/nvidia/mcp55/reset.c: outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); ./southbridge/nvidia/mcp55/reset.c: outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); ./southbridge/nvidia/ck804/reset.c: outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); ./southbridge/nvidia/ck804/reset.c: outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); ./southbridge/intel/sch/reset.c: outb(0x04, 0xcf9); ./southbridge/intel/sch/reset.c: outb(0x02, 0xcf9); ./southbridge/intel/sch/reset.c: outb(0x06, 0xcf9); ./southbridge/intel/i82801ex/reset.c: outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); ./southbridge/intel/i82801bx/reset.c: outb((1 << 2) | (1 << 1), 0xcf9); ./southbridge/intel/i82801cx/reset.c: outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); ./southbridge/intel/i82801gx/reset.c: outb(0x04, 0xcf9); ./southbridge/intel/i82801gx/reset.c: outb((1 << 2) | (1 << 1), 0xcf9); ./southbridge/intel/i82801gx/reset.c: outb(0x02, 0xcf9); ./southbridge/intel/i82801gx/reset.c: outb(0x06, 0xcf9); ./southbridge/intel/i82801dx/reset.c: outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); ./southbridge/intel/i82801ax/reset.c: outb((1 << 2) | (1 << 1), 0xcf9); ./southbridge/intel/i82371eb/i82371eb.h:#define RC 0xcf9 /* Reset control register */ ./southbridge/intel/esb6300/reset.c: outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); ./southbridge/intel/i3100/reset.c: outb(0x06, 0xcf9); ./southbridge/sis/sis966/reset.c: outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); ./southbridge/sis/sis966/reset.c: outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); ./southbridge/amd/sb700/reset.c: outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); ./southbridge/amd/sb700/reset.c: outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); ./southbridge/amd/sb600/reset.c: outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); ./southbridge/amd/sb600/reset.c: outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); ./southbridge/broadcom/bcm5785/reset.c: outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); ./southbridge/broadcom/bcm5785/reset.c: outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); ./mainboard/intel/eagleheights/reset.c: outb(0x04, 0xcf9); ./mainboard/intel/eagleheights/reset.c: outb(0x06, 0xcf9); ./mainboard/intel/jarrell/reset.c: outb(0x04, 0xcf9); ./mainboard/intel/jarrell/reset.c: outb(0x02, 0xcf9); ./mainboard/intel/jarrell/reset.c: outb(0x06, 0xcf9); ./mainboard/intel/jarrell/reset.c: outb(0x0e, 0xcf9); ./mainboard/via/epia-m700/romstage.c: outb(6, 0xcf9); ./mainboard/supermicro/x6dhr_ig2/reset.c: outb(0x04, 0xcf9); ./mainboard/supermicro/x6dhr_ig2/reset.c: outb(0x02, 0xcf9); ./mainboard/supermicro/x6dhr_ig2/reset.c: outb(0x06, 0xcf9); ./mainboard/supermicro/x6dhe_g/reset.c: outb(0x04, 0xcf9); ./mainboard/supermicro/x6dhe_g/reset.c: outb(0x02, 0xcf9); ./mainboard/supermicro/x6dhe_g/reset.c: outb(0x06, 0xcf9); ./mainboard/supermicro/x6dhe_g2/reset.c: outb(0x04, 0xcf9); ./mainboard/supermicro/x6dhe_g2/reset.c: outb(0x02, 0xcf9); ./mainboard/supermicro/x6dhe_g2/reset.c: outb(0x06, 0xcf9); ./mainboard/supermicro/x6dai_g/reset.c: outb(0x04, 0xcf9); ./mainboard/supermicro/x6dai_g/reset.c: outb(0x02, 0xcf9); ./mainboard/supermicro/x6dai_g/reset.c: outb(0x06, 0xcf9); ./mainboard/supermicro/x6dhr_ig/reset.c: outb(0x04, 0xcf9); ./mainboard/supermicro/x6dhr_ig/reset.c: outb(0x02, 0xcf9); ./mainboard/supermicro/x6dhr_ig/reset.c: outb(0x06, 0xcf9); ./mainboard/roda/rk886ex/romstage.c: outb(0x6, 0xcf9); ./mainboard/ibase/mb899/romstage.c: outb(0x6, 0xcf9); ./mainboard/getac/p470/romstage.c: outb(0x6, 0xcf9); ./mainboard/kontron/986lcd-m/romstage.c: outb(0x6, 0xcf9); ./mainboard/dell/s1850/romstage.c: outb(2, 0xcf9); ./mainboard/dell/s1850/romstage.c: outb(6, 0xcf9); ./mainboard/dell/s1850/reset.c: outb(0x04, 0xcf9); ./mainboard/dell/s1850/reset.c: outb(0x02, 0xcf9); ./mainboard/dell/s1850/reset.c: outb(0x06, 0xcf9);