Pete Batard wrote:
]Also, if it's not too much to ask and if the code works without ]FORCE_PANIC, I wouldn't mind finding out where it breaks if not using ]the 48 MHz init (using forced base/type/ldn). ] ]I have now committed your patch to svn. Will still need to figure out ]what the best approach might be with regards to 48 MHz SIO init.
Hello Pete,
I do not have that board setup at the moment so I cannot try it without FORCE_PANIC. It seems like a baud rate change could substitute for the LPC clock frequency programming, but so far that does not work as expected.
I have an AMD SB900 board with Nuvoton NCT6776F. To make the serial port work on this board, two pieces of non-generic code are needed.
1) SIO com1 pins default to GPIO and must switched to serial port use: // logical device 2 (UART A) defaults to base 3f8, irq 4, enabled // all that is needed for early serial is to switch some dual function // pins from gpio use (default) to serial port use. Clearing cr2a bit 7 // does this. u8 reg8; pnp_enter_ext_func_mode(dev); reg8 = pnp_read_config(dev, 0x2a); reg8 &= ~(1 << 7); pnp_write_config(dev, 0x2a, reg8); pnp_exit_ext_func_mode(dev);
2) LPC clock frequency programming and enable: static void sb900_clocks(void) { u8 reg8; u32 reg32; volatile u32 *acpi_mmio28 = (void *) (0xFED80000 + 0xE00 + 0x28); volatile u32 *acpi_mmio40 = (void *) (0xFED80000 + 0xE00 + 0x40);
// Program AcpiMmioEn to enable MMIO access to ClkDrvSth2, MiscClkCntrl registers outb(0x24, 0xCD6); reg8 = inb(0xCD7); reg8 |= 1; reg8 &= ~(1 << 1); outb(reg8, 0xCD7);
// Program ClkDrvSth2 OSCOUT1_CLK_sel for 48 MHz (default is 14 MHz) reg32 = *acpi_mmio28; reg32 &= ~(7 << 16); reg32 |= 2 << 16; *acpi_mmio28 = reg32;
// Program MiscClkCntrl OSCOUT1_Clk_OutputEn to zero to enable LPC clock reg32 = *acpi_mmio40; reg32 &= ~(1 << 2); // Auxiliary Clock1, OSCOUT1 clock output enable *acpi_mmio40 = reg32; }
Thanks, Scott