[coreboot] [pathc][v2] Fam10 name string

-- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Add CPUID processor name string support for Fam10 CPUs. Signed-off-by: Marc Jones marc.jones@amd.com Index: coreboot-v2/src/cpu/amd/model_10xxx/Config.lb =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/Config.lb 2008-04-23 17:39:11.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/Config.lb 2008-04-23 17:41:28.000000000 -0600 @@ -37,3 +37,5 @@ driver model_10xxx_init.o object update_microcode.o object apic_timer.o +object processor_name.o + Index: coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/model_10xxx_init.c 2008-04-23 17:39:11.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/model_10xxx_init.c 2008-04-23 17:41:28.000000000 -0600 @@ -39,13 +39,13 @@ #include <cpu/amd/model_10xxx_msr.h> extern device_t get_node_pci(u32 nodeid, u32 fn); - +extern int init_processor_name(void); #define MCI_STATUS 0x401 -static inline msr_t rdmsr_amd(u32 index) +msr_t rdmsr_amd(u32 index) { msr_t result; __asm__ __volatile__ ( @@ -57,7 +57,7 @@ } -static inline void wrmsr_amd(u32 index, msr_t msr) +void wrmsr_amd(u32 index, msr_t msr) { __asm__ __volatile__ ( "wrmsr" @@ -99,7 +99,9 @@ /* Enable the local cpu apics */ setup_lapic(); - /* FIXME: Update CPUID name strings here */ + /* Set the processor name string */ + init_processor_name(); + #if CONFIG_LOGICAL_CPUS == 1 siblings = cpuid_ecx(0x80000008) & 0xff; Index: coreboot-v2/src/cpu/amd/model_10xxx/processor_name.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ coreboot-v2/src/cpu/amd/model_10xxx/processor_name.c 2008-04-23 17:41:28.000000000 -0600 @@ -0,0 +1,252 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +/* + * This code sets the Processor Name String for AMD64 CPUs. + * + * Revision Guide for AMD Family 10h Processors + * Publication # 41322 Revision: 3.17 Issue Date: February 2008 + */ + +#include <console/console.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/cpu.h> + +extern void wrmsr_amd(u32 index, msr_t msr); + +/* The maximum length of CPU names is 48 bytes, including the final NULL byte. + * If you change these names your BIOS will _NOT_ pass the AMD validation and + * your mainboard will not be posted on the AMD Recommended Motherboard Website + */ + + +static inline void strcpy(char *dst, char *src) +{ + while (*src) *dst++ = *src++; +} + + +static const struct { + u8 Pg; + u8 NC; + u8 String1; + char const *value; +} String1_socket_F[] = { + {0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 83"}, + {0x00, 0x01, 0x01, "Dual-Core AMD Opteron(tm) Processor 23"}, + {0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 83"}, + {0x00, 0x03, 0x01, "Quad-Core AMD Opteron(tm) Processor 23"}, + {0x00, 0x03, 0x02, "Embedded AMD Opteron(tm) Processor 83"}, + {0x00, 0x03, 0x03, "Embedded AMD Opteron(tm) Processor 23"}, + {0x00, 0x03, 0x04, "Embedded AMD Opteron(tm) Processor 13"}, + {0x00, 0x03, 0x05, "AMD Phenom(tm) FX-"}, + {0x01, 0x01, 0x01, "Embedded AMD Opteron(tm) Processor"}, +}; + + +static const struct { + u8 Pg; + u8 NC; + u8 String2; + char const *value; +} String2_socket_F[] = { + {0x00, 0xFF, 0x0A, " SE"}, + {0x00, 0xFF, 0x0B, " HE"}, + {0x00, 0xFF, 0x0C, " EE"}, + {0x00, 0xFF, 0x0D, " Quad-Core Processor"}, + {0x00, 0xFF, 0x0F, ""}, + {0x01, 0x01, 0x01, "GF HE"}, +}; + + +static const struct { + u8 Pg; + u8 NC; + u8 String1; + char const *value; +} String1_socket_AM2[] = { + {0x00, 0x00, 0x00, "AMD Athlon(tm) Processor LE-"}, + {0x00, 0x00, 0x01, "AMD Sempron(tm) Processor LE-"}, + {0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 13"}, + {0x00, 0x01, 0x01, "AMD Athlon(tm)"}, + {0x00, 0x02, 0x00, "AMD Phenom(tm)"}, + {0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 13"}, + {0x00, 0x03, 0x01, "AMD Phenom(tm) FX-"}, + {0x00, 0x03, 0x02, "AMD Phenom(tm)"}, +}; + + +static const struct { + u8 Pg; + u8 NC; + u8 String2; + char const *value; +} String2_socket_AM2[] = { + {0x00, 0x00, 0x00, "00"}, + {0x00, 0x00, 0x01, "10"}, + {0x00, 0x00, 0x02, "20"}, + {0x00, 0x00, 0x03, "30"}, + {0x00, 0x00, 0x04, "40"}, + {0x00, 0x00, 0x05, "50"}, + {0x00, 0x00, 0x06, "60"}, + {0x00, 0x00, 0x07, "70"}, + {0x00, 0x00, 0x08, "80"}, + {0x00, 0x00, 0x09, "90"}, + {0x00, 0x01, 0x00, "00 Dual-Core Processor"}, + {0x00, 0x01, 0x01, "00e Dual-Core Processor"}, + {0x00, 0x01, 0x02, "00B Dual-Core Processor"}, + {0x00, 0x01, 0x03, "50 Dual-Core Processor"}, + {0x00, 0x01, 0x04, "50e Dual-Core Processor"}, + {0x00, 0x01, 0x05, "50B Dual-Core Processor"}, + {0x00, 0x02, 0x00, "00 Triple-Core Processor"}, + {0x00, 0x02, 0x01, "00e Triple-Core Processor"}, + {0x00, 0x02, 0x02, "00B Triple-Core Processor"}, + {0x00, 0x02, 0x03, "50 Triple-Core Processor"}, + {0x00, 0x02, 0x04, "50e Triple-Core Processor"}, + {0x00, 0x02, 0x05, "50B Triple-Core Processor"}, + {0x00, 0x03, 0x00, "00 Quad-Core Processor"}, + {0x00, 0x03, 0x01, "00e Quad-Core Processor"}, + {0x00, 0x03, 0x02, "00B Quad-Core Processor"}, + {0x00, 0x03, 0x03, "50 Quad-Core Processor"}, + {0x00, 0x03, 0x04, "50e Quad-Core Processor"}, + {0x00, 0x03, 0x05, "50B Quad-Core Processor"}, + {0x00, 0x03, 0x0A, " SE"}, + {0x00, 0x03, 0x0B, " HE"}, + {0x00, 0x03, 0x0C, " EE"}, + {0x00, 0x03, 0x0D, " Quad-Core Processor"}, + {0x00, 0xFF, 0x0F, ""}, +}; + + +char const *unknown = "AMD Processor model unknown"; +char const *sample = "AMD Engineering Sample"; +char const *thermal = "AMD Thermal Test Kit"; + + +int init_processor_name(void) +{ + /* variable names taken from fam10 revision guide for clarity */ + u32 BrandId; /* CPUID Fn8000_0001_EBX */ + u8 String1; /* BrandID[14:11] */ + u8 String2; /* BrandID[3:0] */ + u8 Model; /* BrandID[10:4] */ + u8 Pg; /* BrandID[15] */ + u8 PkgTyp; /* CPUID Fn8000_0001_EBX.*/ + u8 NC; /* CPUID Fn8000_0008[ECX].*/ + char *processor_name_string = NULL; + char program_string[48]; + u32 *p_program_string = (u32 *)program_string; + msr_t msr; + int i, j; + + + /* Find out which CPU brand it is */ + BrandId = cpuid_ebx(0x80000001); + String1 = (u8)((BrandId >> 11) & 0x0F); + String2 = (u8)((BrandId >> 0) & 0x0F); + Model = (u8)((BrandId >> 4) & 0xFF); + Pg = (u8)((BrandId >> 15) & 0x01); + PkgTyp = (u8)((BrandId >> 28) & 0x0F); + NC = (u8)(cpuid_ecx(0x80000008) & 0xFF); + + /* null the string */ + memset(program_string, 0, 48); + + if (Model > 0) { + /* String1 */ + if (PkgTyp == 0) { /* F1207 */ + for(i = 0; i < sizeof(String1_socket_F)/sizeof(String1_socket_F[0]); i++) { + if ((String1_socket_F[i].Pg == Pg) && + (String1_socket_F[i].NC == NC) && + (String1_socket_F[i].String1 == String1)) { + processor_name_string = String1_socket_F[i].value; + } + } + } else if (PkgTyp == 1) { /* AM2 */ + for(i = 0; i < sizeof(String1_socket_AM2)/sizeof(String1_socket_AM2[0]); i++) { + if ((String1_socket_AM2[i].Pg == Pg) && + (String1_socket_AM2[i].NC == NC) && + (String1_socket_AM2[i].String1 == String1)) { + processor_name_string = String1_socket_AM2[i].value; + } + } + } + + if (processor_name_string) { + strcpy(program_string, processor_name_string); + + /* Translate Model from 01-99 to ASCII and put it on the end. + * Numbers less than 10 should include a leading zero, e.g., 09.*/ + for (j = 0; j < 47; j++) { + if(program_string[j] == 0) { + program_string[j++] = (Model / 10) + '0'; + program_string[j++] = (Model % 10) + '0'; + break; + } + } + /* String 2 */ + processor_name_string = NULL; + + if (PkgTyp == 0) { /* F1207 */ + for(i = 0; i < sizeof(String2_socket_F)/sizeof(String2_socket_F[0]); i++) { + if ((String2_socket_F[i].Pg == Pg) && + (String2_socket_F[i].String2 == String2)) { + processor_name_string = String2_socket_F[i].value; + } + } + + } else if (PkgTyp == 1) { /* AM2 */ + for(i = 0; i < sizeof(String2_socket_AM2)/sizeof(String2_socket_AM2[0]); i++) { + if ((String2_socket_AM2[i].Pg == Pg) && + (String2_socket_AM2[i].NC == NC) && + (String2_socket_AM2[i].String2 == String2)) { + processor_name_string = String2_socket_AM2[i].value; + } + } + } + + if (processor_name_string) { + /* FIXME: check length but it should never happen */ + strcpy(&program_string[j], processor_name_string); + } + + } else { + processor_name_string = unknown; + strcpy(program_string, processor_name_string); + } + } else { + if (Pg) + processor_name_string = sample; + else + processor_name_string = thermal; + + } + + printk_debug("CPU model: %s\n", program_string); + + for (i = 0; i < 6; i++) { + msr.lo = p_program_string[(2 * i) + 0]; + msr.hi = p_program_string[(2 * i) + 1]; + wrmsr_amd(0xC0010030 + i, msr); + } + + return 0; +} +