Re: [coreboot] flashrom: State of development

[Carl-Daniel Hailfinger]

On 08.05.2009 03:05, Carl-Daniel Hailfinger wrote:
> Hi,
>
> the following flashrom patches from me are pending:
> SB600 SPI hang fix. Needs a test on SPI and a test on LPC.

Ward may test on Monday with a SB600 LPC board if he has time. If anyone
else can test, I'd appreciate it.
> VIA/ICH SPI workaround for standalone WRITE_ENABLE opcodes. This fix
>
> is URGENT. The bug already messed up flash contents of one machine.

Committed.
> SPI one-byte write support. This fix is URGENT. The bug already messed
>
> up flash contents of one machine.

Committed.
> ICH SPI delay change. Reduces a multi-hour flashing of an 8 Mbit chip
>
> on ICH/VIA to one minute.

Waiting for Ack.
> Generic SPI chip detection.

Waiting for Ack.
> JEDEC probe check whether we really read the ID or just flash chip
>
> contents.

Waiting for Ack.
> Better error handling in ICH SPI.

Waiting for Ack.
> Generic block-wise erase infrastructure.

Waiting for Ack.
> Block-wise erase for a dozen chips.

Waiting for Ack.
> Multiple probe functions per chip preparation (e.g. RDID, REMS, RES
>
> for SPI).

Waiting for Ack.
> Explicit read functions for all chips. Needed for external flasher
>
> support.

Committed.
> External flasher infrastructure ready for hooking up.

Committed.
> Some of them have been waiting for an ack since over 6 months, some are
> brand new.
> I appreciate reviews. Resending patches is possible if needed.

Regards,
Carl-Daniel