Ok. Now I've got two lines of output in the serial port from coreboot. Thank you very much. The way I got it is a dodge but at least maybe I can now add debug messages to find the proper way. I just replaced sb700_lpc_init by the corresponding code by Rudolf Marek in the serialICE mainboard .
I can see two differences at first sight: seriaICE uses absolute pci address while sb700_lpc_init looks for PCI Ids, and serialICE writes all the bits of the registers while sb700_lpc_init changes just one bit. Besides, sb700_lpc_init initializes smbus also and does more stuff.
On Tue, Aug 03, 2010 at 12:31:01AM +0200, Rudolf Marek wrote:
Well please investigate because I put there already - it is the write to reg 0x72. There might be watchdog in SB700 datasheet says disabled by default but dunno if there is some possibility that it is enabled by default by some strap resistor.
Aparently it's active.
Make sure you call sb700_lpc_init _before_ any access to superIO.
Looking at coreboot there were (at least) two places where watchdogs get killed (or something like it). One is the one you put in serialICE and the other is inside sb700_lpc_init :
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS contro\ ller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! * This bit has no meaning if debug strap is not enabled. So if the * board keeps rebooting and the code fails to reach here, we could * disable the debug strap first. */ reg32 = pci_read_config32(dev, 0x4C); reg32 |= 1 << 31; pci_write_config32(dev, 0x4C, reg32);
But the odd thing is that when coreboot has output to the serial port (once, no reboot) this code was not running. So I don't see why it doesn't reboot like serialICE. Maybe it simply has hanged before the timeout (but aren't the watchdogs meant to prevent just this?). A hang is not surprising since I removed quite a lot of initialisation from sb700_lpc_init .
I could try to add code similar to that above to serialICE and see what happens.