I have dug into more documentation, and found partial answer.
I am only considering SST flash chips. From the SST Product Selection Guide, among various flash memories(Series 27,37,28,29,25), only SST29xE featured with page-by-page write operations, with a page size of 128 bytes.
Questions: 1. How do we decide the page-sizes of other SST(and other vendors) flash chips, which have no page mechanism? 2. Since we operate the flash chips (in case of ich) with ich_spi_read/write, which in turn call ich_spi_read/write_page, what happens to those chips without a page-read/write operation? I am going to investigate the source code and data sheets further, but it is appreciated if anyone familiar with this tell me directly (and it would guide me through the investigation).
Thanks, yu ning