On 05.03.2018 12:02, Mark Wylde wrote:
Thanks Nico for taking your valuable time to answer my questions. I really appreciate it, and knowing that it should be possible makes me feel better about continuing the project.
I've ordered another display that has better matching specifications. I'll reply here to let others know if it works or not although I agree this is probably not a coreboot issue.
Well that though might have come too hasty. There is some board specific information that coreboot might miss, e.g. how many lanes are actually implemented. If the original display needed only a single DP lane, maybe they omitted the traces for the other lanes (in your log, coreboot tries to train 2 lanes). And maybe there is more that I didn't consider.
A log of the successful training with the original display might give more clues. In case you haven't tried yet, you can probably also let Linux do the DP training. And last but not least, there is a edp_debug() definition at the top of `soc/rockchip/common/edp.c`.
Nico