* Darmawan Salihun darmawan.salihun@gmail.com [070712 09:19]:
Another note that I have difficulty in limiting the direct I/O access in the current driver because I don't know exactly which port to give access to and which one to block. Below is what I've found from the current flashrom code so far. I/O port usage:
0x2E (Winbond W836_INDEX port) 0x2F (Winbond W836_DATA port) 0x4E 0x4F
4e and 4f are superio ports, too
0xC6F 0xCD6 0xCD7
not sure. acpi something?
0xCFC - 0xCFF (PCI I/O port on x86)
a "base + 0x4D" in Via Epia motherboard
base is the interesting thing here.. It's determined dynamically.
0xE800 (what port is this? ) 0xE801 0xE802 0xE803 0xE804 0xE807
I think these are hard codes of some legacy bios setting and should be read dynamically, too..
0xE1 0xEB 0xFF
Wow, what are these?
I don't think you can easily limit this. I am working on support for a board where the final IO address is read dynamically from PCI register space. This might be required on more boards in the future.
I couldn't conclude the the I/O port ranges to open from the portlist above because there is still unknown (I think it's dynamically relocatable) I/O port such as the one used by EPIA board. Any explanation on this issue?