5 Oct
2009
5 Oct
'09
4:07 p.m.
Hi,
we're happy to release coreboot® support for another Kontron embedded mainboard: The Kontron KT690/mITX
http://us.kontron.com/products/boards+and+mezzanines/embedded+motherboards/m...
Best regards,
Stefan Reinauer
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
This patch adds (initial) support for the Kontron KT690 mainboard.
It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU.
Issues with this port:
- hangs early during "Starting Windows" with Windows 7, after loading all the
drivers
- sound is untested and probably not working
- powernow seems to be not working
Signed-off-by: Stefan Reinauer stepan@coresystems.de
Index: src/mainboard/kontron/kt690/fadt.c
===================================================================
--- src/mainboard/kontron/kt690/fadt.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/fadt.c (.../trunk/coreboot-v2)
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <../southbridge/amd/sb600/sb600.h>
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of rs690. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ pm_base &= 0xFFFF;
+ printk_debug("pm_base: 0x%04x\n", pm_base);
+
+ /* Prepare the header */
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (u32) facs;
+ fadt->dsdt = (u32) dsdt;
+ /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+ fadt->preferred_pm_profile = 0x03;
+ fadt->sci_int = 9;
+ /* disable system management mode by setting to 0: */
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0xf0;
+ fadt->acpi_disable = 0xf1;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0xe2;
+
+ pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
+ pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
+ pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
+ pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
+ pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
+ pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
+ pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
+ pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
+
+ /* CpuControl is in _PR.CPU0, 6 bytes */
+ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
+ pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
+
+ pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
+ pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
+
+ pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
+ pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
+
+ pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+ * the contents of the PM registers at
+ * index 20-2B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
+
+ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ fadt->pm1b_evt_blk = 0x0000;
+ fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1b_cnt_blk = 0x0000;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+ fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+ fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 101;
+ fadt->p_lvl3_lat = 1001;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0; /* 0x7d these have to be */
+ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
+ fadt->century = 0; /* 0x7f to make rtc alrm work */
+ fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
+ fadt->flags = 0x0001c1a5;/* 0x25; */
+
+ fadt->res2 = 0;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (u32) facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32) dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 4;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 2;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 32;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}
Index: src/mainboard/kontron/kt690/Config.lb
===================================================================
--- src/mainboard/kontron/kt690/Config.lb (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/Config.lb (.../trunk/coreboot-v2)
@@ -0,0 +1,269 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+##
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#dir /drivers/si/3114
+
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE
+ object get_bus_conf.o
+ object irq_tables.o
+end
+
+if CONFIG_HAVE_ACPI_TABLES
+ object acpi_tables.o
+ object fadt.o
+ makerule dsdt.c
+ depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
+ action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
+ action "mv dsdt.hex dsdt.c"
+ end
+ object ./dsdt.o
+end
+
+#object reset.o
+
+ if CONFIG_USE_INIT
+
+ makerule ./cache_as_ram_auto.o
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
+ end
+
+ else
+
+ makerule ./cache_as_ram_auto.inc
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ end
+
+ end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ end
+
+ if CONFIG_USE_INIT
+ ldscript /cpu/amd/car/cache_as_ram.lds
+ end
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+ ##
+ ## Setup Cache-As-Ram
+ ##
+ mainboardinit cpu/amd/car/cache_as_ram.inc
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+ if CONFIG_USE_INIT
+ initobject cache_as_ram_auto.o
+ else
+ mainboardinit ./cache_as_ram_auto.inc
+ end
+
+##
+## Include the secondary Configuration files
+##
+config chip.h
+
+#The variables belong to mainboard are defined here.
+
+#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#Define gfx_dual_slot, 0: single slot, 1: dual slot
+#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
+#Define gfx_tmds, 0: didn't support TMDS, 1: support
+#Define gfx_compliance, 0: didn't support compliance, 1: support
+#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
+#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_S1G1
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # southbridge
+ chip southbridge/amd/rs690
+ device pci 0.0 on end # HT 0x7910
+ device pci 1.0 on # Internal Graphics P2P bridge 0x7912
+ chip drivers/pci/onboard
+ device pci 5.0 on end # Internal Graphics 0x791F
+ register "rom_address" = "0xfff00000"
+ end
+ end
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+ device pci 3.0 off end # PCIE P2P bridge 0x791b
+ device pci 4.0 on end # PCIE P2P bridge 0x7914
+ device pci 5.0 on end # PCIE P2P bridge 0x7915
+ device pci 6.0 on end # PCIE P2P bridge 0x7916
+ device pci 7.0 on end # PCIE P2P bridge 0x7917
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ register "vga_rom_address" = "0xfff00000"
+ register "gpp_configuration" = "4"
+ register "port_enable" = "0xfc"
+ register "gfx_dev2_dev3" = "1"
+ register "gfx_dual_slot" = "0"
+ register "gfx_lane_reversal" = "0"
+ register "gfx_tmds" = "0"
+ register "gfx_compliance" = "0"
+ register "gfx_reconfiguration" = "1"
+ register "gfx_link_width" = "0"
+ end
+ chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+ device pci 12.0 on end # SATA 0x4380
+ device pci 13.0 on end # USB 0x4387
+ device pci 13.1 on end # USB 0x4388
+ device pci 13.2 on end # USB 0x4389
+ device pci 13.3 on end # USB 0x438a
+ device pci 13.4 on end # USB 0x438b
+ device pci 13.5 on end # USB 2 0x4386
+ device pci 14.0 on # SM 0x4385
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x438c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x438d
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ #device pnp 2e.6 off # SPI
+ #end
+ device pnp 2e.7 off # GPIO
+ end
+ device pnp 2e.8 on # WDTO#, PLED
+ end
+ device pnp 2e.9 off # GPIO
+ end
+ device pnp 2e.a off # ACPI
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xa10
+ end
+ device pnp 2e.c off # PECI, SST
+ end
+ end #superio/winbond/w83627dhg
+ #chip superio/smsc/fdc37n972
+ # seems this chip is not used?
+ #end
+ end #LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # ACI 0x4382
+ device pci 14.6 on end # MCI 0x438e
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "hda_viddid" = "0x10ec0888"
+ end #southbridge/amd/sb600
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #northbridge/amd/amdk8
+ end #pci_domain
+end #northbridge/amd/amdk8/root_complex
+
Index: src/mainboard/kontron/kt690/devicetree.cb
===================================================================
--- src/mainboard/kontron/kt690/devicetree.cb (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/devicetree.cb (.../trunk/coreboot-v2)
@@ -0,0 +1,132 @@
+#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#Define gfx_dual_slot, 0: single slot, 1: dual slot
+#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
+#Define gfx_tmds, 0: didn't support TMDS, 1: support
+#Define gfx_compliance, 0: didn't support compliance, 1: support
+#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
+#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_S1G1
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # southbridge
+ chip southbridge/amd/rs690
+ device pci 0.0 on end # HT 0x7910
+ device pci 1.0 on # Internal Graphics P2P bridge 0x7912
+ chip drivers/pci/onboard
+ device pci 5.0 on end # Internal Graphics 0x791F
+ register "rom_address" = "0xfff00000"
+ end
+ end
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+ device pci 3.0 off end # PCIE P2P bridge 0x791b
+ device pci 4.0 on end # PCIE P2P bridge 0x7914
+ device pci 5.0 on end # PCIE P2P bridge 0x7915
+ device pci 6.0 on end # PCIE P2P bridge 0x7916
+ device pci 7.0 on end # PCIE P2P bridge 0x7917
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ register "vga_rom_address" = "0xfff00000"
+ register "gpp_configuration" = "4"
+ register "port_enable" = "0xfc"
+ register "gfx_dev2_dev3" = "1"
+ register "gfx_dual_slot" = "0"
+ register "gfx_lane_reversal" = "0"
+ register "gfx_tmds" = "0"
+ register "gfx_compliance" = "0"
+ register "gfx_reconfiguration" = "1"
+ register "gfx_link_width" = "0"
+ end
+ chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+ device pci 12.0 on end # SATA 0x4380
+ device pci 13.0 on end # USB 0x4387
+ device pci 13.1 on end # USB 0x4388
+ device pci 13.2 on end # USB 0x4389
+ device pci 13.3 on end # USB 0x438a
+ device pci 13.4 on end # USB 0x438b
+ device pci 13.5 on end # USB 2 0x4386
+ device pci 14.0 on # SM 0x4385
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x438c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x438d
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ #device pnp 2e.6 off # SPI
+ #end
+ device pnp 2e.7 off # GPIO
+ end
+ device pnp 2e.8 on # WDTO#, PLED
+ end
+ device pnp 2e.9 off # GPIO
+ end
+ device pnp 2e.a off # ACPI
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xa10
+ end
+ device pnp 2e.c off # PECI, SST
+ endif
+
+ end #superio/winbond/w83627dhg
+ #chip superio/smsc/fdc37n972
+ #end
+ end #LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # ACI 0x4382
+ device pci 14.6 on end # MCI 0x438e
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "hda_viddid" = "0x10ec0888"
+ end #southbridge/amd/sb600
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #northbridge/amd/amdk8
+ end #pci_domain
+end #northbridge/amd/amdk8/root_complex
+
Index: src/mainboard/kontron/kt690/mptable.c
===================================================================
--- src/mainboard/kontron/kt690/mptable.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/mptable.c (.../trunk/coreboot-v2)
@@ -0,0 +1,212 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern u8 bus_isa;
+extern u8 bus_rs690[8];
+extern u8 bus_sb600[2];
+
+extern u32 apicid_sb600;
+
+extern u32 bus_type[256];
+extern u32 sbdn_rs690;
+extern u32 sbdn_sb600;
+
+extern void get_bus_conf(void);
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "KONTRON ";
+ static const char productid[12] = "KT690 ";
+ struct mp_config_table *mc;
+ int j;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+
+ /* Bus: Bus ID Type */
+ /* define bus and isa numbers */
+ for (j = 0; j < bus_isa; j++) {
+ smp_write_bus(mc, j, (char *)"PCI ");
+ }
+ smp_write_bus(mc, bus_isa, (char *)"ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ {
+ device_t dev;
+ u32 dword;
+ u8 byte;
+
+ dev =
+ dev_find_slot(bus_sb600[0],
+ PCI_DEVFN(sbdn_sb600 + 0x14, 0));
+ if (dev) {
+ dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+
+ /* Initialize interrupt mapping */
+ /* aza */
+ byte = pci_read_config8(dev, 0x63);
+ byte &= 0xf8;
+ byte |= 0; /* 0: INTA, ...., 7: INTH */
+ pci_write_config8(dev, 0x63, byte);
+
+ /* SATA */
+ dword = pci_read_config32(dev, 0xac);
+ dword &= ~(7 << 26);
+ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ /* dword |= 1<<22; PIC and APIC co exists */
+ pci_write_config32(dev, 0xac, dword);
+
+ /*
+ * 00:12.0: PROG SATA : INT F
+ * 00:13.0: INTA USB_0
+ * 00:13.1: INTB USB_1
+ * 00:13.2: INTC USB_2
+ * 00:13.3: INTD USB_3
+ * 00:13.4: INTC USB_4
+ * 00:13.5: INTD USB2
+ * 00:14.1: INTA IDE
+ * 00:14.2: Prog HDA : INT E
+ * 00:14.5: INTB ACI
+ * 00:14.6: INTB MCI
+ */
+ }
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
+
+ /* ISA ints are edge-triggered, and usually originate from the ISA bus,
+ * or its remainings.
+ */
+#define ISA_INT(intr, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin))
+
+ ISA_INT(0x1, 0x1);
+ ISA_INT(0x0, 0x2);
+ ISA_INT(0x3, 0x3);
+ ISA_INT(0x4, 0x4);
+ ISA_INT(0x6, 0x6);
+ ISA_INT(0x7, 0x7);
+ ISA_INT(0xc, 0xc);
+ ISA_INT(0xd, 0xd);
+ ISA_INT(0xe, 0xe);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#if CONFIG_HAVE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+ /* usb */
+ PCI_INT(0x0, 0x13, 0x0, 0x10);
+ PCI_INT(0x0, 0x13, 0x1, 0x11);
+ PCI_INT(0x0, 0x13, 0x2, 0x12);
+ PCI_INT(0x0, 0x13, 0x3, 0x13);
+
+ /* sata */
+ PCI_INT(0x0, 0x12, 0x0, 0x16);
+
+ /* HD Audio: b0:d20:f1:reg63 should be 0. */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* on board NIC & Slot PCIE. */
+ PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
+ PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
+ PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
+ PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
+ PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
+ PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
+ PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
+ PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
+
+ /* PCI slots */
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
+ PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
+ PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
+ PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
+ PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
+ PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
+ PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum =
+ smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/kontron/kt690/irq_tables.c
===================================================================
--- src/mainboard/kontron/kt690/irq_tables.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/irq_tables.c (.../trunk/coreboot-v2)
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern void get_bus_conf(void);
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_rs690[8];
+extern u8 bus_sb600[2];
+extern unsigned long sbdn_sb600;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_sb600[0];
+ pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk_info("write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
Index: src/mainboard/kontron/kt690/resourcemap.c
===================================================================
--- src/mainboard/kontron/kt690/resourcemap.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/resourcemap.c (.../trunk/coreboot-v2)
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static void setup_kt690_resource_map(void)
+{
+ static const unsigned int register_values[] = {
+ /* Careful set limit registers before base registers which contain the enables */
+ /* DRAM Limit i Registers
+ * F1:0x44 i = 0
+ * F1:0x4C i = 1
+ * F1:0x54 i = 2
+ * F1:0x5C i = 3
+ * F1:0x64 i = 4
+ * F1:0x6C i = 5
+ * F1:0x74 i = 6
+ * F1:0x7C i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 3] Reserved
+ * [10: 8] Interleave select
+ * specifies the values of A[14:12] to use with interleave enable.
+ * [15:11] Reserved
+ * [31:16] DRAM Limit Address i Bits 39-24
+ * This field defines the upper address bits of a 40 bit address
+ * that define the end of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+ PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+ PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+ PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+ PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+ PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+ /* DRAM Base i Registers
+ * F1:0x40 i = 0
+ * F1:0x48 i = 1
+ * F1:0x50 i = 2
+ * F1:0x58 i = 3
+ * F1:0x60 i = 4
+ * F1:0x68 i = 5
+ * F1:0x70 i = 6
+ * F1:0x78 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 7: 2] Reserved
+ * [10: 8] Interleave Enable
+ * 000 = No interleave
+ * 001 = Interleave on A[12] (2 nodes)
+ * 010 = reserved
+ * 011 = Interleave on A[12] and A[14] (4 nodes)
+ * 100 = reserved
+ * 101 = reserved
+ * 110 = reserved
+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+ * [15:11] Reserved
+ * [13:16] DRAM Base Address i Bits 39-24
+ * This field defines the upper address bits of a 40-bit address
+ * that define the start of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+ /* Memory-Mapped I/O Limit i Registers
+ * F1:0x84 i = 0
+ * F1:0x8C i = 1
+ * F1:0x94 i = 2
+ * F1:0x9C i = 3
+ * F1:0xA4 i = 4
+ * F1:0xAC i = 5
+ * F1:0xB4 i = 6
+ * F1:0xBC i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = Reserved
+ * [ 6: 6] Reserved
+ * [ 7: 7] Non-Posted
+ * 0 = CPU writes may be posted
+ * 1 = CPU writes must be non-posted
+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+ * This field defines the upp adddress bits of a 40-bit address that
+ * defines the end of a memory-mapped I/O region n
+ */
+ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+ /* Memory-Mapped I/O Base i Registers
+ * F1:0x80 i = 0
+ * F1:0x88 i = 1
+ * F1:0x90 i = 2
+ * F1:0x98 i = 3
+ * F1:0xA0 i = 4
+ * F1:0xA8 i = 5
+ * F1:0xB0 i = 6
+ * F1:0xB8 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Cpu Disable
+ * 0 = Cpu can use this I/O range
+ * 1 = Cpu requests do not use this I/O range
+ * [ 3: 3] Lock
+ * 0 = base/limit registers i are read/write
+ * 1 = base/limit registers i are read-only
+ * [ 7: 4] Reserved
+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+ * This field defines the upper address bits of a 40bit address
+ * that defines the start of memory-mapped I/O region i
+ */
+ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+ /* PCI I/O Limit i Registers
+ * F1:0xC4 i = 0
+ * F1:0xCC i = 1
+ * F1:0xD4 i = 2
+ * F1:0xDC i = 3
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = reserved
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Limit Address i
+ * This field defines the end of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+ /* PCI I/O Base i Registers
+ * F1:0xC0 i = 0
+ * F1:0xC8 i = 1
+ * F1:0xD0 i = 2
+ * F1:0xD8 i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 3: 2] Reserved
+ * [ 4: 4] VGA Enable
+ * 0 = VGA matches Disabled
+ * 1 = matches all address < 64K and where A[9:0] is in the
+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+ * [ 5: 5] ISA Enable
+ * 0 = ISA matches Disabled
+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+ * from matching agains this base/limit pair
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Base i
+ * This field defines the start of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+ /* Config Base and Limit i Registers
+ * F1:0xE0 i = 0
+ * F1:0xE4 i = 1
+ * F1:0xE8 i = 2
+ * F1:0xEC i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Device Number Compare Enable
+ * 0 = The ranges are based on bus number
+ * 1 = The ranges are ranges of devices on bus 0
+ * [ 3: 3] Reserved
+ * [ 6: 4] Destination Node
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 7] Reserved
+ * [ 9: 8] Destination Link
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 - Reserved
+ * [15:10] Reserved
+ * [23:16] Bus Number Base i
+ * This field defines the lowest bus number in configuration region i
+ * [31:24] Bus Number Limit i
+ * This field defines the highest bus number in configuration regin i
+ */
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+ };
+
+ int max;
+ max = ARRAY_SIZE(register_values);
+ setup_resource_map(register_values, max);
+}
Index: src/mainboard/kontron/kt690/Options.lb
===================================================================
--- src/mainboard/kontron/kt690/Options.lb (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/Options.lb (.../trunk/coreboot-v2)
@@ -0,0 +1,310 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+## Copyright (C) 2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+##
+##
+
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CBFS
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CONFIG_CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_USE_PRINTK_IN_CAR
+
+uses CONFIG_VIDEO_MB
+uses CONFIG_GFXUMA
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
+
+###
+### Build options
+###
+
+##
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+##
+default CONFIG_ROM_SIZE=524288
+
+##
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+#256K
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+
+##
+## Build code for the fallback boot
+##
+default CONFIG_HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from coreboot
+##
+default CONFIG_HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default CONFIG_HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+default CONFIG_HAVE_ACPI_TABLES=1
+
+##
+## Build code to export a CMOS option table
+##
+default CONFIG_HAVE_OPTION_TABLE=0
+
+##
+## Move the default coreboot cmos range off of AMD RTC registers
+##
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+
+default CONFIG_MAX_PHYSICAL_CPUS=1
+default CONFIG_LOGICAL_CPUS=1
+
+#1G memory hole
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+# BTDC: Only one HT device on Herring.
+#HT Unit ID offset
+#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_UNITID_BASE=0x0
+
+
+#real SB Unit ID
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
+
+#make the SB HT chain on bus 0
+default CONFIG_SB_HT_CHAIN_ON_BUS0=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default CONFIG_MAINBOARD_PART_NUMBER="KT690"
+default CONFIG_MAINBOARD_VENDOR="KONTRON"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1488
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6900
+
+
+###
+### coreboot layout values
+###
+
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 32K stack
+##
+default CONFIG_STACK_SIZE=0x8000
+
+##
+## Use a small 32K heap
+##
+default CONFIG_HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+
+##
+## coreboot C code runs at this location in RAM
+##
+default CONFIG_RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
+
+# Select the serial console base port
+default CONFIG_TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default CONFIG_TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## CONFIG_DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+default CONFIG_VIDEO_MB=1
+default CONFIG_GFXUMA=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
+
+### End Options.lb
+#
+# CBFS
+#
+#
+default CONFIG_CBFS=1
+end
Index: src/mainboard/kontron/kt690/acpi_tables.c
===================================================================
--- src/mainboard/kontron/kt690/acpi_tables.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi_tables.c (.../trunk/coreboot-v2)
@@ -0,0 +1,291 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+#include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
+#include <arch/cpu.h>
+#include <cpu/amd/model_fxx_powernow.h>
+
+extern u16 pm_base;
+
+#define DUMP_ACPI_TABLES 0
+
+/*
+* Assume the max pstate number is 8
+* 0x21(33 bytes) is one package length of _PSS package
+*/
+
+#define Maxpstate 8
+#define Defpkglength 0x21
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+ u32 i;
+ print_debug("dump_mem:");
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
+ printk_debug("\n%08x:", i);
+ }
+ printk_debug(" %02x", (u8)*((u8 *)i));
+ }
+ print_debug("\n");
+}
+#endif
+
+extern u8 AmlCode[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern u8 AmlCode_ssdt2[];
+extern u8 AmlCode_ssdt3[];
+extern u8 AmlCode_ssdt4[];
+extern u8 AmlCode_ssdt5[];
+#endif
+
+#define IO_APIC_ADDR 0xfec00000UL
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB600 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+ /* create all subtables for processors */
+ /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+extern void get_bus_conf(void);
+
+void update_ssdtx(void *ssdtx, int i)
+{
+ uint8_t *PCI;
+ uint8_t *HCIN;
+ uint8_t *UID;
+
+ PCI = ssdtx + 0x32;
+ HCIN = ssdtx + 0x39;
+ UID = ssdtx + 0x40;
+
+ if (i < 7) {
+ *PCI = (uint8_t) ('4' + i - 1);
+ } else {
+ *PCI = (uint8_t) ('A' + i - 1 - 6);
+ }
+ *HCIN = (uint8_t) i;
+ *UID = (uint8_t) (i + 3);
+
+ /* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) {
+ k8acpi_write_vars();
+ amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+ /* Align ACPI tables to 16byte */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk_debug("ACPI: * HPET\n");
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ printk_debug("ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+#if 0
+ /* SRAT */
+ printk_debug("ACPI: * SRAT\n");
+ srat = (acpi_srat_t *) current;
+ acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+
+ /* SLIT */
+ printk_debug("ACPI: * SLIT\n");
+ slit = (acpi_slit_t *) current;
+ acpi_create_slit(slit);
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+#endif
+
+ /* SSDT */
+ printk_debug("ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+
+ acpi_create_ssdt_generator(ssdt, "DYNADATA");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+ /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
+
+ for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
+ if ((sysconf.pci1234[i] & 1) != 1)
+ continue;
+ uint8_t c;
+ if (i < 7) {
+ c = (uint8_t) ('4' + i - 1);
+ } else {
+ c = (uint8_t) ('A' + i - 1 - 6);
+ }
+ printk_debug("ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
+ current = (current + 0x07) & -0x08;
+ ssdtx = (acpi_header_t *) current;
+ switch (sysconf.hcid[i]) {
+ case 1: /* 8132 */
+ p = AmlCode_ssdt2;
+ break;
+ case 2: /* 8151 */
+ p = AmlCode_ssdt3;
+ break;
+ case 3: /* 8131 */
+ p = AmlCode_ssdt4;
+ break;
+ default:
+ /* HTX no io apic */
+ p = AmlCode_ssdt5;
+ break;
+ }
+ current += ((acpi_header_t *) p)->length;
+ memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *) p)->length);
+ update_ssdtx((void *)ssdtx, i);
+ ssdtx->checksum = 0;
+ ssdtx->checksum =
+ acpi_checksum((u8 *)ssdtx, ssdtx->length);
+ acpi_add_table(rsdp, ssdtx);
+ }
+#endif
+
+ /* FACS */
+ printk_debug("ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* DSDT */
+ printk_debug("ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy((void *)dsdt, (void *)AmlCode,
+ ((acpi_header_t *) AmlCode)->length);
+ current += dsdt->length;
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+ /* FADT */
+ printk_debug("ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+ printk_debug("rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk_debug("rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk_debug("madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk_debug("srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk_debug("slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk_debug("ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk_debug("fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+ printk_info("ACPI: done.\n");
+ return current;
+}
Index: src/mainboard/kontron/kt690/chip.h
===================================================================
--- src/mainboard/kontron/kt690/chip.h (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/chip.h (.../trunk/coreboot-v2)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config
+{
+ u32 uma_size; /* How many UMA should be used in memory for TOP. */
+};
+
Index: src/mainboard/kontron/kt690/acpi/globutil.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/globutil.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/globutil.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+Scope(_SB) {
+ Include ("globutil.asl")
+}
+*/
+
+/* string compare functions */
+Method(MIN, 2)
+{
+ if (LLess(Arg0, Arg1)) {
+ Return(Arg0)
+ } else {
+ Return(Arg1)
+ }
+}
+
+Method(SLEN, 1)
+{
+ Store(Arg0, Local0)
+ Return(Sizeof(Local0))
+}
+
+Method(S2BF, 1)
+{
+ Add(SLEN(Arg0), One, Local0)
+ Name(BUFF, Buffer(Local0) {})
+ Store(Arg0, BUFF)
+ Return(BUFF)
+}
+
+/* Strong string compare. Checks both length and content */
+Method(SCMP, 2)
+{
+ Store(S2BF(Arg0), Local0)
+ Store(S2BF(Arg1), Local1)
+ Store(Zero, Local4)
+ Store(SLEN(Arg0), Local5)
+ Store(SLEN(Arg1), Local6)
+ Store(MIN(Local5, Local6), Local7)
+
+ While(LLess(Local4, Local7)) {
+ Store(Derefof(Index(Local0, Local4)), Local2)
+ Store(Derefof(Index(Local1, Local4)), Local3)
+ if (LGreater(Local2, Local3)) {
+ Return(One)
+ } else {
+ if (LLess(Local2, Local3)) {
+ Return(Ones)
+ }
+ }
+ Increment(Local4)
+ }
+ if (LLess(Local4, Local5)) {
+ Return(One)
+ } else {
+ if (LLess(Local4, Local6)) {
+ Return(Ones)
+ } else {
+ Return(Zero)
+ }
+ }
+}
+
+/* Weak string compare. Checks to find Arg1 at beginning of Arg0.
+* Fails if length(Arg0) < length(Arg1). Returns 0 on Fail, 1 on
+* Pass.
+*/
+Method(WCMP, 2)
+{
+ Store(S2BF(Arg0), Local0)
+ Store(S2BF(Arg1), Local1)
+ if (LLess(SLEN(Arg0), SLEN(Arg1))) {
+ Return(0)
+ }
+ Store(Zero, Local2)
+ Store(SLEN(Arg1), Local3)
+
+ While(LLess(Local2, Local3)) {
+ if (LNotEqual(Derefof(Index(Local0, Local2)),
+ Derefof(Index(Local1, Local2)))) {
+ Return(0)
+ }
+ Increment(Local2)
+ }
+ Return(One)
+}
+
+/* ARG0 = IRQ Number(0-15)
+* Returns Bit Map
+*/
+Method(I2BM, 1)
+{
+ Store(0, Local0)
+ if (LNotEqual(ARG0, 0)) {
+ Store(1, Local1)
+ ShiftLeft(Local1, ARG0, Local0)
+ }
+ Return(Local0)
+}
Index: src/mainboard/kontron/kt690/acpi/ide.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/ide.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/ide.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ Include ("ide.asl")
+ }
+ }
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+ Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+ PPTS, 8, /* Primary PIO Slave Timing */
+ PPTM, 8, /* Primary PIO Master Timing */
+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
+ PMTM, 8, /* Primary MWDMA Master Timing */
+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
+ PPSM, 4, /* Primary PIO slave Mode */
+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
+ PDSM, 4, /* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
+ Increment(Local0)
+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
+ Increment(Local1)
+ Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+ Name (_ADR, Zero)
+ Method(_GTM, 0)
+ {
+ NAME(OTBF, Buffer(20) { /* out buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+ /* Just return if the channel is disabled */
+ If(And(PPCR, 0x01)) { /* primary PIO control */
+ Return(OTBF)
+ }
+
+ /* Always tell them independent timing available and IOChannelReady used on both drives */
+ Or(BFFG, 0x1A, BFFG)
+
+ Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
+ Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
+
+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */
+ Or(BFFG, 0x01, BFFG)
+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+ }
+ Else {
+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
+ }
+
+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */
+ Or(BFFG, 0x04, BFFG)
+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+ }
+ Else {
+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
+ }
+
+ Return(OTBF) /* out buffer */
+ } /* End Method(_GTM) */
+
+ Method(_STM, 3, NotSerialized)
+ {
+ NAME(INBF, Buffer(20) { /* in buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDMM,)
+ Or(PDCR, 0x01, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTM)
+ }
+ }
+
+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDSM,)
+ Or(PDCR, 0x02, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTS)
+ }
+ }
+ /* Return(INBF) */
+ } /*End Method(_STM) */
+ Device(MST)
+ {
+ Name(_ADR, 0)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xA0, CMDA)
+ Store(0xA0, CMDB)
+ Store(0xA0, CMDC)
+
+ Or(PPMM, 0x08, POMD)
+
+ If(And(PDCR, 0x01)) {
+ Or(PDMM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTM),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(MST) */
+
+ Device(SLAV)
+ {
+ Name(_ADR, 1)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xB0, CMDA)
+ Store(0xB0, CMDB)
+ Store(0xB0, CMDC)
+
+ Or(PPSM, 0x08, POMD)
+
+ If(And(PDCR, 0x02)) {
+ Or(PDSM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTS),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(SLAV) */
+}
Index: src/mainboard/kontron/kt690/acpi/debug.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/debug.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/debug.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ DefinitionBlock (
+ "DSDT.AML",
+ "DSDT",
+ 0x01,
+ "XXXXXX",
+ "XXXXXXXX",
+ 0x00010001
+ )
+ {
+ Include ("debug.asl")
+ }
+*/
+
+/*
+* 0x80: POST_BASE
+* 0x3F8: DEBCOM_BASE
+* X80: POST_REGION
+* P80: PORT80
+*
+* CREG: DEBCOM_REGION
+* CUAR: DEBCOM_UART
+* CDAT: DEBCOM_DATA
+* CDLM: DEBCOM_DLM
+* DLCR: DEBCOM_LCR
+* CMCR: DEBCOM_MCR
+* CLSR: DEBCOM_LSR
+*
+* DEBUG_INIT DINI
+*/
+
+OperationRegion(X80, SystemIO, 0x80, 1)
+ Field(X80, ByteAcc, NoLock, Preserve)
+{
+ P80, 8
+}
+
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+ Field(CREG, ByteAcc, NoLock, Preserve)
+{
+ CDAT, 8,
+ CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
+}
+
+/*
+* DINI
+* Initialize the COM port to 115,200 8-N-1
+*/
+Method(DINI)
+{
+ store(0x83, DLCR)
+ store(0x01, CDAT) /* 115200 baud (low) */
+ store(0x00, CDLM) /* 115200 baud (high) */
+ store(0x03, DLCR) /* word=8 stop=1 parity=none */
+ store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */
+ store(0x00, CDLM) /* turn off interrupts */
+}
+
+/*
+* THRE
+* Wait for COM port transmitter holding register to go empty
+*/
+Method(THRE)
+{
+ and(CLSR, 0x20, local0)
+ while (Lequal(local0, Zero)) {
+ and(CLSR, 0x20, local0)
+ }
+}
+
+/*
+* OUTX
+* Send a single raw character
+*/
+Method(OUTX, 1)
+{
+ THRE()
+ store(Arg0, CDAT)
+}
+
+/*
+* OUTC
+* Send a single character, expanding LF into CR/LF
+*/
+Method(OUTC, 1)
+{
+ if (LEqual(Arg0, 0x0a)) {
+ OUTX(0x0d)
+ }
+ OUTX(Arg0)
+}
+
+/*
+* DBGN
+* Send a single hex nibble
+*/
+Method(DBGN, 1)
+{
+ and(Arg0, 0x0f, Local0)
+ if (LLess(Local0, 10)) {
+ add(Local0, 0x30, Local0)
+ } else {
+ add(Local0, 0x37, Local0)
+ }
+ OUTC(Local0)
+}
+
+/*
+* DBGB
+* Send a hex byte
+*/
+Method(DBGB, 1)
+{
+ ShiftRight(Arg0, 4, Local0)
+ DBGN(Local0)
+ DBGN(Arg0)
+}
+
+/*
+* DBGW
+* Send a hex word
+*/
+Method(DBGW, 1)
+{
+ ShiftRight(Arg0, 8, Local0)
+ DBGB(Local0)
+ DBGB(Arg0)
+}
+
+/*
+* DBGD
+* Send a hex Dword
+*/
+Method(DBGD, 1)
+{
+ ShiftRight(Arg0, 16, Local0)
+ DBGW(Local0)
+ DBGW(Arg0)
+}
+
+/*
+* DBGO
+* Send either a string or an integer
+*/
+Method(DBGO, 1)
+{
+ /* DINI() */
+ if (LEqual(ObjectType(Arg0), 1)) {
+ if (LGreater(Arg0, 0xffff)) {
+ DBGD(Arg0)
+ } else {
+ if (LGreater(Arg0, 0xff)) {
+ DBGW(Arg0)
+ } else {
+ DBGB(Arg0)
+ }
+ }
+ } else {
+ Name(BDBG, Buffer(80) {})
+ store(Arg0, BDBG)
+ store(0, Local1)
+ while (One) {
+ store(GETC(BDBG, Local1), Local0)
+ if (LEqual(Local0, 0)) {
+ return (0)
+ }
+ OUTC(Local0)
+ Increment(Local1)
+ }
+ }
+ return (0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+ CreateByteField(Arg0, Arg1, DBGC)
+ return (DBGC)
+}
Index: src/mainboard/kontron/kt690/acpi/routing.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/routing.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/routing.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,262 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ Include ("routing.asl")
+ }
+*/
+
+/* Routing is in System Bus scope */
+Scope(_SB) {
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - RS690 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, INTD, 0 },
+ Package(){0x0003FFFF, 1, INTA, 0 },
+ Package(){0x0003FFFF, 2, INTB, 0 },
+ Package(){0x0003FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, INTB, 0 },
+ Package(){0x0005FFFF, 1, INTC, 0 },
+ Package(){0x0005FFFF, 2, INTD, 0 },
+ Package(){0x0005FFFF, 3, INTA, 0 },
+
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ Package(){0x0006FFFF, 0, INTC, 0 },
+ Package(){0x0006FFFF, 1, INTD, 0 },
+ Package(){0x0006FFFF, 2, INTA, 0 },
+ Package(){0x0006FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0007FFFF, 0, INTD, 0 },
+ Package(){0x0007FFFF, 1, INTA, 0 },
+ Package(){0x0007FFFF, 2, INTB, 0 },
+ Package(){0x0007FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices */
+ /* Bus 0, Dev 17 - SATA controller #2 */
+ /* Bus 0, Dev 18 - SATA controller #1 */
+ Package(){0x0012FFFF, 1, INTA, 0 }, // Link G?
+
+ /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+ Package(){0x0013FFFF, 0, INTA, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+ Package(){0x0013FFFF, 2, INTC, 0 },
+ Package(){0x0013FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - RS690 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){ 0x0002FFFF, 0, 0, 18 },
+ Package(){ 0x0002FFFF, 1, 0, 19 },
+ Package(){ 0x0002FFFF, 2, 0, 16 },
+ Package(){ 0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){ 0x0003FFFF, 0, 0, 19 },
+ Package(){ 0x0003FFFF, 1, 0, 16 },
+ Package(){ 0x0003FFFF, 2, 0, 17 },
+ Package(){ 0x0003FFFF, 3, 0, 18 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){ 0x0004FFFF, 0, 0, 16 },
+ Package(){ 0x0004FFFF, 1, 0, 17 },
+ Package(){ 0x0004FFFF, 2, 0, 18 },
+ Package(){ 0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){ 0x0005FFFF, 0, 0, 17 },
+ Package(){ 0x0005FFFF, 1, 0, 18 },
+ Package(){ 0x0005FFFF, 2, 0, 19 },
+ Package(){ 0x0005FFFF, 3, 0, 16 },
+
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ Package(){ 0x0006FFFF, 0, 0, 18 },
+ Package(){ 0x0006FFFF, 1, 0, 19 },
+ Package(){ 0x0006FFFF, 2, 0, 16 },
+ Package(){ 0x0006FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ Package(){ 0x0007FFFF, 0, 0, 19 },
+ Package(){ 0x0007FFFF, 1, 0, 16 },
+ Package(){ 0x0007FFFF, 2, 0, 17 },
+ Package(){ 0x0007FFFF, 3, 0, 18 },
+
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 17 - SATA controller #2 */
+ /* Bus 0, Dev 18 - SATA controller #1 */
+ Package(){ 0x0012FFFF, 0, 0, 22 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+ Package(){ 0x0013FFFF, 0, 0, 16 },
+ Package(){ 0x0013FFFF, 1, 0, 17 },
+ Package(){ 0x0013FFFF, 2, 0, 18 },
+ Package(){ 0x0013FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
+ Package(){ 0x0014FFFF, 0, 0, 16 },
+ Package(){ 0x0014FFFF, 1, 0, 17 },
+ Package(){ 0x0014FFFF, 2, 0, 18 },
+ Package(){ 0x0014FFFF, 3, 0, 19 },
+
+ })
+
+ Name(PR1, Package(){
+ /* Internal graphics - RS690 VGA, Bus1, Dev5 */
+ Package(){0x0005FFFF, 0, INTC, 0 },
+ Package(){0x0005FFFF, 1, INTD, 0 },
+ Package(){0x0005FFFF, 2, INTA, 0 },
+ Package(){0x0005FFFF, 3, INTB, 0 },
+ })
+
+ Name(APR1, Package(){
+ /* Internal graphics - RS690 VGA, Bus1, Dev5 */
+ Package(){0x0005FFFF, 0, 0, 18 },
+ Package(){0x0005FFFF, 1, 0, 19 },
+ Package(){0x0005FFFF, 2, 0, 16 },
+ Package(){0x0005FFFF, 3, 0, 17 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ Package(){0x0006FFFF, 0, 0, 0x15 },
+ Package(){0x0006FFFF, 1, 0, 0x16 },
+ Package(){0x0006FFFF, 2, 0, 0x17 },
+ Package(){0x0006FFFF, 3, 0, 0x14 },
+ Package(){0x0007FFFF, 0, 0, 0x16 },
+ Package(){0x0007FFFF, 1, 0, 0x17 },
+ Package(){0x0007FFFF, 2, 0, 0x14 },
+ Package(){0x0007FFFF, 3, 0, 0x15 },
+ })
+}
Index: src/mainboard/kontron/kt690/acpi/sata.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/sata.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/sata.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00120000)
+ Include ("sata.asl")
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ _GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (_SB.P0PR) {
+ if (LGreater(_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, _SB.P0PR)
+ }
+
+ if (_SB.P1PR) {
+ if (LGreater(_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, _SB.P1PR)
+ }
+
+ if (_SB.P2PR) {
+ if (LGreater(_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, _SB.P2PR)
+ }
+
+ if (_SB.P3PR) {
+ if (LGreater(_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, _SB.P3PR)
+ }
+ }
+}
Index: src/mainboard/kontron/kt690/acpi/usb.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/usb.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/usb.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ Include ("usb.asl")
+ }
+*/
+Method(UCOC, 0) {
+ Sleep(20)
+ Store(0x13,CMTI)
+ Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+ Scope (_GPE) {
+ Method (_L13) {
+ UCOC()
+ if(LEqual(GPB0,PLC0)) {
+ Not(PLC0,PLC0)
+ Store(PLC0, _SB.PT0D)
+ }
+ }
+ }
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+ Scope (_GPE) {
+ Method (_L14) {
+ UCOC()
+ if (LEqual(GPB1,PLC1)) {
+ Not(PLC1,PLC1)
+ Store(PLC1, _SB.PT1D)
+ }
+ }
+ }
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+ Scope (_GPE) {
+ Method (_L15) {
+ UCOC()
+ if (LEqual(GPB2,PLC2)) {
+ Not(PLC2,PLC2)
+ Store(PLC2, _SB.PT2D)
+ }
+ }
+ }
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+ Scope (_GPE) {
+ Method (_L16) {
+ UCOC()
+ if (LEqual(GPB3,PLC3)) {
+ Not(PLC3,PLC3)
+ Store(PLC3, _SB.PT3D)
+ }
+ }
+ }
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+ Scope (_GPE) {
+ Method (_L19) {
+ UCOC()
+ if (LEqual(GPB4,PLC4)) {
+ Not(PLC4,PLC4)
+ Store(PLC4, _SB.PT4D)
+ }
+ }
+ }
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+ Scope (_GPE) {
+ Method (_L1A) {
+ UCOC()
+ if (LEqual(GPB5,PLC5)) {
+ Not(PLC5,PLC5)
+ Store(PLC5, _SB.PT5D)
+ }
+ }
+ }
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+ Scope (_GPE) {
+ /* Method (_L1C) { */
+ Method (_L06) {
+ UCOC()
+ if (LEqual(GPB6,PLC6)) {
+ Not(PLC6,PLC6)
+ Store(PLC6, _SB.PT6D)
+ }
+ }
+ }
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ Scope (_GPE) {
+ /* Method (_L1D) { */
+ Method (_L07) {
+ UCOC()
+ if (LEqual(GPB7,PLC7)) {
+ Not(PLC7,PLC7)
+ Store(PLC7, _SB.PT7D)
+ }
+ }
+ }
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+ Scope (_GPE) {
+ Method (_L17) {
+ if (LEqual(G8IS,PLC8)) {
+ Not(PLC8,PLC8)
+ Store(PLC8, _SB.PT8D)
+ }
+ }
+ }
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+ Scope (_GPE) {
+ Method (_L0E) {
+ if (LEqual(G9IS,0)) {
+ Store(1,_SB.PT9D)
+ }
+ }
+ }
+}
Index: src/mainboard/kontron/kt690/acpi/doit.sh
===================================================================
--- src/mainboard/kontron/kt690/acpi/doit.sh (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/doit.sh (.../trunk/coreboot-v2)
@@ -0,0 +1,3 @@
+#!/bin/bash
+#cpp -P dsdt.asl > dsdt.i
+iasl dsdt.asl
Index: src/mainboard/kontron/kt690/acpi/statdef.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/statdef.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/statdef.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+/* Status and notification definitions */
+
+#define STA_MISSING 0x00
+#define STA_PRESENT 0x01
+#define STA_ENABLED 0x03
+#define STA_DISABLED 0x09
+#define STA_INVISIBLE 0x0B
+#define STA_UNAVAILABLE 0x0D
+#define STA_VISIBLE 0x0F
+
+/* SMBus status codes */
+#define SMB_OK 0x00
+#define SMB_UnknownFail 0x07
+#define SMB_DevAddrNAK 0x10
+#define SMB_DeviceError 0x11
+#define SMB_DevCmdDenied 0x12
+#define SMB_UnknownErr 0x13
+#define SMB_DevAccDenied 0x17
+#define SMB_Timeout 0x18
+#define SMB_HstUnsuppProtocol 0x19
+#define SMB_Busy 0x1A
+#define SMB_PktChkError 0x1F
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK 0x00
+#define NOTIFY_DEVICE_CHECK 0x01
+#define NOTIFY_DEVICE_WAKE 0x02
+#define NOTIFY_EJECT_REQUEST 0x03
+#define NOTIFY_DEVICE_CHECK_JR 0x04
+#define NOTIFY_FREQUENCY_ERROR 0x05
+#define NOTIFY_BUS_MODE 0x06
+#define NOTIFY_POWER_FAULT 0x07
+#define NOTIFY_CAPABILITIES 0x08
+#define NOTIFY_PLD_CHECK 0x09
+#define NOTIFY_SLIT_UPDATE 0x0B
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG 0x80
+#define NOTIFY_BAT_INFOCHG 0x81
+#define NOTIFY_BAT_MAINTDATA 0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG 0x80
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG 0x80
+#define NOTIFY_TZ_TRIPPTCHG 0x81
+#define NOTIFY_TZ_DEVLISTCHG 0x82
+#define NOTIFY_TZ_RELTBLCHG 0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON 0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON 0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG 0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG 0x80
+#define NOTIFY_CPU_CSTATECHG 0x81
+#define NOTIFY_CPU_THROTLCHG 0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG 0x80
+
+/* Battery Device Notification Values */
+#define NOTIFY_ALS_ILLUMCHG 0x80
+#define NOTIFY_ALS_COLORTMPCHG 0x81
+#define NOTIFY_ALS_RESPCHG 0x82
+
+
Index: src/mainboard/kontron/kt690/acpi/dsdt.asl
===================================================================
--- src/mainboard/kontron/kt690/acpi/dsdt.asl (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/acpi/dsdt.asl (.../trunk/coreboot-v2)
@@ -0,0 +1,1791 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "dsdt.aml", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "COREv2", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* Include ("debug.asl") */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ Scope(_SB) {
+
+ /* PCIe Configuration Space for 16 busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve)
+ {
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ Include ("routing.asl")
+
+ Scope(_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ _SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized)
+ {
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKA\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKA\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKA\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKA\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKB\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKB\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKB\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKB\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKC\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKC\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKC\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKC\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKD\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKD\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKD\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKD\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKE\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKE\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKE\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKE\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKF\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKF\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKF\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKF\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKG\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKG\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKG\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKG\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\_SB\LNKH\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\_SB\LNKH\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\_SB\LNKH\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\_SB\LNKH\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * _PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(_PTS, 1) {
+ /* DBGO("\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(_SB.SBRI, 0x13)) {
+ * Store(0,_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ _SB.PCI0.SIOS (Arg0)
+ } /* End Method(_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * _GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(_GTS, 1) {
+ * DBGO("\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * _BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(_BFS, 1) {
+ /* DBGO("\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * _WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(_WAK, 1) {
+ /* DBGO("\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ _SB.PCI0.SIOW (Arg0)
+ Return(WKST)
+ } /* End Method(_WAK) */
+
+ Scope(_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\_GPE\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\_GPE\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\_GPE\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\_GPE\_L00\n") */
+ Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\_GPE\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\_GPE\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\_GPE\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\_GPE\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\_GPE\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\_GPE\_L09\n") */
+ Notify (_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\_GPE\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\_GPE\_L0B\n") */
+ Notify(_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\_GPE\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\_GPE\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\_GPE\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\_GPE\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\_GPE\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\_GPE\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\_GPE\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\_GPE\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\_GPE\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\_GPE\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\_GPE\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\_GPE\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\_GPE\_L18\n") */
+ Notify(_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\_GPE\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\_GPE\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\_GPE\_L1B\n") */
+ Notify(_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\_GPE\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\_GPE\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\_GPE\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\_GPE\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ Include ("usb.asl")
+
+ /* South Bridge */
+ Scope(_SB) { /* Start _SB scope */
+ Include ("globutil.asl") /* global utility methods expected within the _SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\_SB\PCI0\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The internal GFX bridge */
+ Device(AGPB) {
+ Name(_ADR, 0x00010000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ Return (APR1)
+ }
+ } /* end AGPB */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge, not used in Herring */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00120000)
+ Include ("sata.asl")
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ Include ("ide.asl")
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\_SB\PCI0\LpcIsaBr\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device(HPTM) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS,ResourceTemplate() {
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ })
+ Method(_STA, 0) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0) {
+ CreateDwordField(CRS, ^HPT._BAS, HPBA)
+ Store(HPBA, HPBA)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ /* ITE IT8712F Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
+ }
+
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
+
+ /* Enter the IT8712F MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* IT8712F magic number */
+ }
+ /* Exit the IT8712F MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+
+ /*
+ * Keyboard PME is routed to SB600 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("IT8712F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
+ }
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
+
+ /* DRAM Memory from 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
+
+ /* BIOS space just below 4GB */
+ DWORDMemory(
+ ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PCBM
+ )
+
+ /* DRAM memory from 4GB to TopMem2 */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ DMHI
+ )
+
+ /* BIOS space just below 16EB */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PEBM
+ )
+
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\_SB\PCI0\_CRS\n") */
+
+ CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+ CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+ CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+ CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+ CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+ CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+ CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+ CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+ CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+ If(LGreater(LOMH, 0xC0000)){
+ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
+ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
+ }
+
+ /* Set size of memory from 1MB to TopMem */
+ Subtract(TOM1, 0x100000, DMLL)
+
+ /*
+ * If(LNotEqual(TOM2, 0x00000000)){
+ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
+ * Subtract(TOM2, 0x100000000, DMHL)
+ * }
+ */
+
+ /* If there is no memory above 4GB, put the BIOS just below 4GB */
+ If(LEqual(TOM2, 0x00000000)){
+ Store(PBAD,PBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+ }
+ Else { /* Otherwise, put the BIOS just below 16EB */
+ ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,EBML)
+ }
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\_SB\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \_OS=") */
+ /* DBGO(_OS) */
+ /* DBGO("\n \_REV=") */
+ /* DBGO(_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End _SB scope */
+
+ Scope(_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\_SI\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ Mutex (SBX0, 0x00)
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 800)
+ Name (TCRT, 850)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\_TZ\TZ00\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\_TZ\TZ00\_AL0\n") */
+ Return(Package() {_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\_TZ\TZ00\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\_TZ\TZ00\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\_TZ\TZ00\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\_TZ\TZ00\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+ If (LGreater (Local0, 0x10)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400, KELV))
+ }
+
+ Store (SMBR (0x07, 0x4C, 0x01), Local0)
+ /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+ /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+ If (LGreater (Local0, 0x10)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
Index: src/mainboard/kontron/kt690/cmos.layout
===================================================================
--- src/mainboard/kontron/kt690/cmos.layout (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/cmos.layout (.../trunk/coreboot-v2)
@@ -0,0 +1,119 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+##
+##
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 dual_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 reserved_memory
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
Index: src/mainboard/kontron/kt690/mainboard.c
===================================================================
--- src/mainboard/kontron/kt690/mainboard.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/mainboard.c (.../trunk/coreboot-v2)
@@ -0,0 +1,257 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <../southbridge/amd/sb600/sb600.h>
+#include "chip.h"
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+#define SMBUS_IO_BASE 0x1000
+
+extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
+ u8 val);
+extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
+ uint64_t start, uint64_t size);
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+uint64_t uma_memory_base, uma_memory_size;
+
+/********************************************************
+* dbm690t uses a BCM5789 as on-board NIC.
+* It has a pin named LOW_POWER to enable it into LOW POWER state.
+* In order to run NIC, we should let it out of Low power state. This pin is
+* controlled by sb600 GPM3.
+* RRG4.2.3 GPM as GPIO
+* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
+* I/O C50, C51, C52, PM I/O94, 95, 96.
+* RRG4.2.3.1 GPM pins as Input
+* RRG4.2.3.2 GPM pins as Output
+********************************************************/
+static void enable_onboard_nic()
+{
+ u8 byte;
+
+ printk_info("%s.\n", __func__);
+
+ /* set index register 0C50h to 13h (miscellaneous control) */
+ outb(0x13, 0xC50); /* CMIndex */
+
+ /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
+ byte = inb(0xC51);
+ byte &= 0x3F;
+ byte |= 0x40;
+ outb(byte, 0xC51);
+
+ /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
+ byte = inb(0xC52);
+ byte &= ~0x8;
+ outb(byte, 0xC52);
+
+ /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
+ byte = inb(0xC51);
+ byte &= 0x3F;
+ byte |= 0x80; /* 7:6=10 */
+ outb(byte, 0xC51);
+
+ /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
+ byte = inb(0xC52);
+ byte &= ~0x8;
+ outb(byte, 0xC52);
+}
+
+/********************************************************
+* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66()
+{
+ u8 byte;
+ struct device *sm_dev;
+ struct device *ide_dev;
+
+ printk_info("%s.\n", __func__);
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb600 settings for thermal config */
+ /* set SB600 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in dbm690t board.
+* This function called early than rs690_enable.
+*************************************************/
+void kt690_enable(device_t dev)
+{
+ struct mainboard_config *mainboard =
+ (struct mainboard_config *)dev->chip_info;
+
+ printk_info("Mainboard KT690 Enable. dev=0x%p\n", dev);
+
+#if (CONFIG_GFXUMA == 1)
+ msr_t msr, msr2;
+
+ /* TOP_MEM: the top of DRAM below 4G */
+ msr = rdmsr(TOP_MEM);
+ printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr.lo, msr.hi);
+
+ /* TOP_MEM2: the top of DRAM above 4G */
+ msr2 = rdmsr(TOP_MEM2);
+ printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+ __func__, msr2.lo, msr2.hi);
+
+ switch (msr.lo) {
+ case 0x10000000: /* 256M system memory */
+ uma_memory_size = 0x2000000; /* 32M recommended UMA */
+ break;
+
+ case 0x18000000: /* 384M system memory */
+ uma_memory_size = 0x4000000; /* 64M recommended UMA */
+ break;
+
+ case 0x20000000: /* 512M system memory */
+ uma_memory_size = 0x4000000; /* 64M recommended UMA */
+ break;
+
+ default: /* 1GB and above system memory */
+ uma_memory_size = 0x8000000; /* 128M recommended UMA */
+ break;
+ }
+
+ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+ __func__, uma_memory_size, uma_memory_base);
+
+ /* TODO: TOP_MEM2 */
+#else
+ uma_memory_size = 0x8000000; /* 128M recommended UMA */
+ uma_memory_base = 0x38000000; /* 1GB system memory supposed */
+#endif
+
+ enable_onboard_nic();
+ get_ide_dma66();
+ set_thermal_config();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ /* UMA is removed from system memory in the northbridge code, but
+ * in some circumstances we want the memory mentioned as reserved.
+ */
+#if (CONFIG_GFXUMA == 1)
+ printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
+ uma_memory_base, uma_memory_size);
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ uma_memory_base, uma_memory_size);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Kontron KT690/mITX Mainboard")
+ .enable_dev = kt690_enable,
+};
Index: src/mainboard/kontron/kt690/cache_as_ram_auto.c
===================================================================
--- src/mainboard/kontron/kt690/cache_as_ram_auto.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/cache_as_ram_auto.c (.../trunk/coreboot-v2)
@@ -0,0 +1,245 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define K8_SET_FIDVID 1
+#define QRANK_DIMM_SUPPORT 1
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+#define RC0 (6<<8)
+#define RC1 (7<<8)
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+
+#define ICS951462_ADDRESS 0x69
+#define SMBUS_HUB 0x71
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+
+#define post_code(x) outb(x, 0x80)
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#include "southbridge/amd/rs690/rs690_early_setup.c"
+#include "southbridge/amd/sb600/sb600_early_setup.c"
+
+/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+/* called in raminit_f.c */
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+/*called in raminit_f.c */
+static inline int spd_read_byte(u32 device, u32 address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "lib/generic_sdram.c"
+#include "resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ /* Is this a cpu only reset? Is this a secondary cpu? */
+ if ((cpu_init_detectedx) || (!boot_cpu())) {
+ if (last_boot_normal()) { /* RTC already inited */
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
+
+ /* sb600_lpc_port80(); */
+ sb600_pci_port80();
+
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+normal_image:
+ post_code(0x23);
+ __asm__ volatile ("jmp __normal_image": /* outputs */
+ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
+
+fallback_image:
+ post_code(0x25);
+}
+#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+ failover_process(bist, cpu_init_detectedx);
+#endif
+ real_main(bist, cpu_init_detectedx);
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ device_t dev;
+ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
+ int needs_reset = 0;
+ u32 bsp_apicid = 0;
+ msr_t msr;
+ struct cpuid_result cpuid1;
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+
+ if (bist == 0) {
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+ }
+
+ enable_rs690_dev8();
+ sb600_lpc_init();
+
+ dev=PNP_DEV(0x2e, W83627DHG_SP1);
+ w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+ printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+
+ setup_kt690_resource_map();
+
+ setup_coherent_ht_domain();
+
+#if CONFIG_LOGICAL_CPUS==1
+ /* It is said that we should start core1 after all core0 launched */
+ wait_all_core0_started();
+ start_other_cores();
+#endif
+ wait_all_aps_started(bsp_apicid);
+
+ ht_setup_chains_x(sysinfo);
+
+ /* run _early_setup before soft-reset. */
+ rs690_early_setup();
+ sb600_early_setup();
+
+ /* Check to see if processor is capable of changing FIDVID */
+ /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+ cpuid1 = cpuid(0x80000007);
+ if( (cpuid1.edx & 0x6) == 0x6 ) {
+
+ /* Read FIDVID_STATUS */
+ msr=rdmsr(0xc0010042);
+ printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+ enable_fid_change();
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+ init_fidvid_bsp(bsp_apicid);
+
+ /* show final fid and vid */
+ msr=rdmsr(0xc0010042);
+ printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+ } else {
+ printk_debug("Changing FIDVID not supported\n");
+ printk_spew("... because cpuid returned %08x\n", cpuid1.edx);
+ }
+
+ needs_reset = optimize_link_coherent_ht();
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ rs690_htinit();
+ printk_debug("needs_reset=0x%x\n", needs_reset);
+
+
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ soft_reset();
+ }
+
+ allow_all_aps_stop(bsp_apicid);
+
+ /* It's the time to set ctrl now; */
+ printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
+ sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+ rs690_before_pci_init();
+ sb600_before_pci_init();
+
+ post_cache_as_ram();
+}
Index: src/mainboard/kontron/kt690/get_bus_conf.c
===================================================================
--- src/mainboard/kontron/kt690/get_bus_conf.c (.../branches/upstream/coreboot-v2)
+++ src/mainboard/kontron/kt690/get_bus_conf.c (.../trunk/coreboot-v2)
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_isa;
+u8 bus_rs690[8];
+u8 bus_sb600[2];
+u32 apicid_sb600;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+ 0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+ 0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_rs690;
+u32 sbdn_sb600;
+
+extern void get_sblk_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+ u32 apicid_base;
+ device_t dev;
+ int i, j;
+
+ if (get_bus_conf_done == 1)
+ return; /* do it only once */
+ get_bus_conf_done = 1;
+
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
+
+ get_sblk_pci1234();
+
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+ sbdn_rs690 = sysconf.sbdn;
+ sbdn_sb600 = 0;
+
+ for (i = 0; i < 2; i++) {
+ bus_sb600[i] = 0;
+ }
+ for (i = 0; i < 8; i++) {
+ bus_rs690[i] = 0;
+ }
+
+ for (i = 0; i < 256; i++) {
+ bus_type[i] = 0; /* default ISA bus. */
+ }
+
+ bus_type[0] = 1; /* pci */
+
+ bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_sb600[0] = bus_rs690[0];
+
+ bus_type[bus_rs690[0]] = 1;
+
+ /* sb600 */
+ dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
+ if (dev) {
+ bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ for (j = bus_sb600[1]; j < bus_isa; j++)
+ bus_type[j] = 1;
+ }
+
+ /* rs690 */
+ for (i = 1; i < 8; i++) {
+ dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
+ if (dev) {
+ bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ if(255 != bus_rs690[i]) {
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ bus_type[bus_rs690[i]] = 1; /* PCI bus. */
+ }
+ }
+ }
+
+ /* I/O APICs: APIC ID Version State Address */
+ bus_isa = 10;
+#if CONFIG_LOGICAL_CPUS==1
+ apicid_base = get_apicid_base(1);
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+ apicid_sb600 = apicid_base + 0;
+}
Index: targets/kontron/kt690/Config-abuild.lb
===================================================================
--- targets/kontron/kt690/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/kontron/kt690/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -0,0 +1,31 @@
+# This will make a target directory of ./VENDOR_MAINBOARD
+
+target VENDOR_MAINBOARD
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
+
+__COMPRESSION__
+__LOGLEVEL__
+
+option CONFIG_ROM_SIZE=1024*1024
+romimage "normal"
+ option CONFIG_USE_FALLBACK_IMAGE=0
+ option CONFIG_ROM_IMAGE_SIZE=0x20000
+ option CONFIG_XIP_ROM_SIZE=0x20000
+ option COREBOOT_EXTRA_VERSION=".0-normal"
+ payload __PAYLOAD__
+end
+
+romimage "fallback"
+ option CONFIG_USE_FALLBACK_IMAGE=1
+ option CONFIG_ROM_IMAGE_SIZE=0x20000
+ option CONFIG_XIP_ROM_SIZE=0x20000
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
+ payload __PAYLOAD__
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
+pci_rom ../../../misc/KT690/pci1002,791f.rom vendor_id=0x1002 device_id=0x791f
Index: targets/kontron/kt690/Config.lb
===================================================================
--- targets/kontron/kt690/Config.lb (.../branches/upstream/coreboot-v2)
+++ targets/kontron/kt690/Config.lb (.../trunk/coreboot-v2)
@@ -0,0 +1,21 @@
+# This will make a target directory of ./dbm690t
+
+target kt690
+mainboard kontron/kt690
+
+romimage "normal"
+ option CONFIG_ROM_SIZE = 1024*1024 - 55808
+ option CONFIG_USE_FALLBACK_IMAGE=0
+ option CONFIG_ROM_IMAGE_SIZE=0x20000
+ option CONFIG_XIP_ROM_SIZE=0x20000
+ payload ../payload.elf
+end
+
+romimage "fallback"
+ option CONFIG_USE_FALLBACK_IMAGE=1
+ option CONFIG_ROM_IMAGE_SIZE=0x20000
+ option CONFIG_XIP_ROM_SIZE=0x20000
+ payload ../payload.elf
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
Index: targets/kontron/kt690/VERSION
===================================================================
--- targets/kontron/kt690/VERSION (.../branches/upstream/coreboot-v2)
+++ targets/kontron/kt690/VERSION (.../trunk/coreboot-v2)
@@ -0,0 +1 @@
+_kt690
coreboot-2.0.0-r2489:2492M.0-fallback Mon Oct 5 13:35:51 CEST 2009 starting...
bsp_apicid=0x0
core0 started:
SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x60fc2.
CPU Rev is K8_G0.
NB Revision is A12.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
Changing FIDVID not supported
needs_reset=0x1
ht reset -
coreboot-2.0.0-r2489:2492M.0-fallback Mon Oct 5 13:35:51 CEST 2009 starting...
bsp_apicid=0x0
core0 started:
SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x60fc2.
CPU Rev is K8_G0.
NB Revision is A12.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
Changing FIDVID not supported
needs_reset=0x0
sysinfo->nodes: 1 sysinfo->ctrl: cf188 spd_addr: ffff8a8c
Ram1.00
Ram2.00
sdram_set_spd_registers: paramx :000cef18
333MHz
Interleaved
RAM end at 0x00080000 kB
Ram3
sdram_enable: tsc0[8]: 000cee00Initializing memory: done
Setting variable MTRR 2, base: 0MB, range: 512MB, type WB
DQS Training:RcvrEn:Pass1: 00
CTLRMaxDelay=00
done
DQS Training:DQSPos: 00
TrainDQSRdWrPos: buf_a:000ce8c0
TrainDQSPos: MutualCSPassW[48] :000ce798
TrainDQSPos: MutualCSPassW[48] :000ce798
TrainDQSPos: MutualCSPassW[48] :000ce798
TrainDQSPos: MutualCSPassW[48] :000ce798
done
DQS Training:RcvrEn:Pass2: 00
CTLRMaxDelay=4c
done
DQS SAVE NVRAM: c2000
DQS Training:tsc[00]=000000000ae60478
DQS Training:tsc[01]=000000000b9b512e
DQS Training:tsc[02]=000000000ba3294d
DQS Training:tsc[03]=000000000f0e3200
DQS Training:tsc[04]=000000000fbbe0ea
Ram4
v_esp=000cef68
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Stage: loading fallback/coreboot_ram @ 0x100000 (393216 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-2.0.0-r2489:2492M.0-fallback Mon Oct 5 13:35:51 CEST 2009 booting...
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 0 resources
PCI: 00:03.0: enabled 0, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:07.0: enabled 1, 0 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:12.0: enabled 1, 0 resources
PCI: 00:13.0: enabled 1, 0 resources
PCI: 00:13.1: enabled 1, 0 resources
PCI: 00:13.2: enabled 1, 0 resources
PCI: 00:13.3: enabled 1, 0 resources
PCI: 00:13.4: enabled 1, 0 resources
PCI: 00:13.5: enabled 1, 0 resources
PCI: 00:14.0: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
PCI: 00:14.1: enabled 1, 0 resources
PCI: 00:14.2: enabled 1, 0 resources
PCI: 00:14.3: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 2 resources
PNP: 002e.2: enabled 1, 2 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.5: enabled 1, 3 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 1, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PNP: 002e.b: enabled 1, 1 resources
PNP: 002e.c: enabled 0, 0 resources
PCI: 00:14.4: enabled 1, 0 resources
PCI: 00:14.5: enabled 1, 0 resources
PCI: 00:14.6: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 0 resources
PCI: 00:03.0: enabled 0, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:07.0: enabled 1, 0 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:12.0: enabled 1, 0 resources
PCI: 00:13.0: enabled 1, 0 resources
PCI: 00:13.1: enabled 1, 0 resources
PCI: 00:13.2: enabled 1, 0 resources
PCI: 00:13.3: enabled 1, 0 resources
PCI: 00:13.4: enabled 1, 0 resources
PCI: 00:13.5: enabled 1, 0 resources
PCI: 00:14.0: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
PCI: 00:14.1: enabled 1, 0 resources
PCI: 00:14.2: enabled 1, 0 resources
PCI: 00:14.3: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 2 resources
PNP: 002e.2: enabled 1, 2 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.5: enabled 1, 3 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 1, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PNP: 002e.b: enabled 1, 1 resources
PNP: 002e.c: enabled 0, 0 resources
PCI: 00:14.4: enabled 1, 0 resources
PCI: 00:14.5: enabled 1, 0 resources
PCI: 00:14.6: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
Mainboard KT690 Enable. dev=0x00122860
kt690_enable, TOP MEM: msr.lo = 0x20000000, msr.hi = 0x00000000
kt690_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
kt690_enable: uma size 0x04000000, memory start 0x1c000000
enable_onboard_nic.
get_ide_dma66.
PCI: Using configuration type 1
Init adt7461 end , status 0x02 fd
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI: 00:18.3 siblings=0
CPU: APIC: 00 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] enabled
rs690_enable: dev=00124ad8, VID_DID=0x79101002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x00124ad8, dev=0x00126d38, port=0x8
PCI: 00:00.0 [1002/7910] enabled
PCI: 00:00.0 [1002/7910] enabled next_unitid: 0015
PCI: pci_scan_bus for bus 00
rs690_enable: dev=00124ad8, VID_DID=0x79101002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x00124ad8, dev=0x00126d38, port=0x8
PCI: 00:00.0 [1002/7910] enabled
rs690_enable: dev=00124f24, VID_DID=0x79121002
Bus-0, Dev-1, Fun-0.
PCI: 00:01.0 [1002/7912] enabled
rs690_enable: dev=00125370, VID_DID=0x79131002
Bus-0, Dev-2,3, Fun-0. enable=1
rs690_gfx_init, nb_dev=0x00124ad8, dev=0x00125370, port=0x2.
rs690_gfx_init step0.
rs690_gfx_init step1.
rs690_gfx_init step2.
rs690_gfx_init step4.
rs690_gfx_init step6.
rs690_gfx_init step8.1.
rs690_gfx_init step8.2.
rs690_gfx_init step8.3.
rs690_gfx_init step8.4.
rs690_gfx_init step8.5.
rs690_gfx_init step8.6.
rs690_gfx_init step8.8.
rs690_gfx_init step8.9.
rs690_gfx_init step8.10.
rs690_gfx_init step8.11.
rs690_gfx_init step8.12.
rs690_gfx_init step8.13.
rs690_gfx_init single_port_configuration.
PcieLinkTraining port=2:lc current state=2030400
rs690_gfx_init single_port_configuration step12.
rs690_gfx_init single_port_configuration step13.
rs690_gfx_init single_port_configuration step14.
Disabling static device: PCI: 00:02.0
rs690_enable: dev=001257bc, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
rs690_enable: dev=00125c08, VID_DID=0x79141002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00124ad8, dev=0x00125c08, port=0x4
PcieLinkTraining port=4:lc current state=4000102
PcieTrainPort port=0x4 result=0
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1002/7914] enabled
rs690_enable: dev=00126054, VID_DID=0x79151002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00124ad8, dev=0x00126054, port=0x5
PcieLinkTraining port=5:lc current state=4000102
PcieTrainPort port=0x5 result=0
PCI: 00:05.0 subordinate bus PCI Express
PCI: 00:05.0 [1002/7915] enabled
rs690_enable: dev=001264a0, VID_DID=0x79161002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00124ad8, dev=0x001264a0, port=0x6
PcieLinkTraining port=6:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=30
PcieTrainPort reg=0x80000000
PcieTrainPort port=0x6 result=1
PCI: 00:06.0 subordinate bus PCI Express
PCI: 00:06.0 [1002/7916] enabled
rs690_enable: dev=001268ec, VID_DID=0x79171002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00124ad8, dev=0x001268ec, port=0x7
PcieLinkTraining port=7:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=38
PcieTrainPort reg=0x80000000
PcieTrainPort port=0x7 result=1
PCI: 00:07.0 subordinate bus PCI Express
PCI: 00:07.0 [1002/7917] enabled
rs690_enable: dev=00126d38, VID_DID=0x79181002
Bus-0, Dev-8, Fun-0. enable=0
disable_pcie_bar3()
sb600_enable()
PCI: 00:12.0 [1002/4380] enabled
sb600_enable()
PCI: 00:13.0 [1002/4387] enabled
sb600_enable()
PCI: 00:13.1 [1002/4388] enabled
sb600_enable()
PCI: 00:13.2 [1002/4389] enabled
sb600_enable()
PCI: 00:13.3 [1002/438a] enabled
sb600_enable()
PCI: 00:13.4 [1002/438b] enabled
sb600_enable()
PCI: 00:13.5 [1002/4386] enabled
sb600_enable()
PCI: 00:14.0 [1002/4385] enabled
sb600_enable()
PCI: 00:14.1 [1002/438c] enabled
sb600_enable()
PCI: 00:14.2 [1002/4383] enabled
sb600_enable()
PCI: 00:14.3 [1002/438d] enabled
sb600_enable()
PCI: 00:14.4 [1002/4384] enabled
sb600_enable()
PCI: 00:14.5 [1002/4382] enabled
sb600_enable()
PCI: 00:14.6 [1002/438e] enabled
PCI: pci_scan_bus for bus 01
rs690_internal_gfx_enable dev=0x00127188, nb_dev=0x00124ad8.
nb_dev, 0x8c=0x10002333
PCI: 01:05.0 [1002/791f] enabled
PCI: 01:05.2 [1002/7919] enabled
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [10ec/8168] enabled
PCI: pci_scan_bus returning with max=004
PCIe: tuning PCI: 04:00.0
PCI: pci_scan_bus for bus 05
PCI: 05:00.0 [10ec/8168] enabled
PCI: pci_scan_bus returning with max=005
PCIe: tuning PCI: 05:00.0
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
PNP: 002e.0 disabled
PNP: 002e.1 disabled
sb600 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
sb600 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
sb600 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
sb600 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
sb600 lpc decode:PNP: 002e.b, base=0x00000a10, end=0x00000a11
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 01
PCI: 00:14.5 subsystem <- 1488/6900
PCI: 00:14.5 cmd <- 02
PCI: 00:14.6 subsystem <- 1488/6900
PCI: 00:14.6 cmd <- 02
PCI: 00:18.1 subsystem <- 1488/6900
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1488/6900
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x0000d000, offset=0x00100000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 60fc2
CPU: family 0f, model 6c, stepping 02
Enabling cache
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base: 0MB, range: 512MB, type WB
Setting variable MTRR 1, base: 512MB, range: 64MB, type WB
Setting variable MTRR 2, base: 448MB, range: 64MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU model Mobile AMD Sempron(tm) Processor 2100+
Setting up local apic... apic_id: 0x00 done.
ECC Disabled
CPU #0 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:00.0 init
pcie_init in rs690_ht.c
PCI: 01:05.0 init
internal_gfx_pci_dev_init device=791f, vendor=1002, vga_rom_address=0xfff00000.
In cbfs, rom address for PCI: 01:05.0 = fff00038
On mainboard, rom address for PCI: 01:05.0 = fff00038
copying VGA ROM Image from fff00038 to 0xc0000, 0xda00 bytes
entering emulator
int15 vector at 0
int15 vector at 0
int15 vector at 0
exited emulator
PCI: 00:12.0 init
No Primary Master SATA drive on Slot0
No Primary Slave SATA drive on Slot1
No Secondary Master SATA drive on Slot2
No Secondary Slave SATA drive on Slot3
PCI: 00:13.0 init
PCI: 00:13.1 init
PCI: 00:13.2 init
PCI: 00:13.3 init
PCI: 00:13.4 init
PCI: 00:13.5 init
usb2_bar0=fc409400
PCI: 00:14.0 init
sm_init().
lapicid = 0000000000000000
set power on after power fail
++++++++++no set NMI+++++
RTC Init
3.11, ABCFG:0x54
3.12, ABCFG:0x54
sm_init() end
PCI: 00:14.1 init
CBFS: Could not find file pci1002,438c.rom
In cbfs, rom address for PCI: 00:14.1 = 00000000
On mainboard, rom address for PCI: 00:14.1 = 0
PCI: 00:14.2 init
base = fc400000
codec_mask = 08
PCI: 00:14.3 init
PNP: 002e.2 init
PNP: 002e.3 init
PNP: 002e.5 init
Keyboard init...
Keyboard selftest failed ACK: 0xfe
PNP: 002e.8 init
PNP: 002e.b init
PCI: 00:14.4 init
PCI: 00:18.1 init
CBFS: Could not find file pci1022,1101.rom
In cbfs, rom address for PCI: 00:18.1 = 00000000
On mainboard, rom address for PCI: 00:18.1 = 0
PCI: 00:18.2 init
CBFS: Could not find file pci1022,1102.rom
In cbfs, rom address for PCI: 00:18.2 = 00000000
On mainboard, rom address for PCI: 00:18.2 = 0
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 01:05.2 init
CBFS: Could not find file pci1002,7919.rom
In cbfs, rom address for PCI: 01:05.2 = 00000000
On card, rom address for PCI: 01:05.2 = 0
PCI: 04:00.0 init
CBFS: Could not find file pci10ec,8168.rom
In cbfs, rom address for PCI: 04:00.0 = 00000000
On card, rom address for PCI: 04:00.0 = fc200000
Incorrect Expansion ROM Header Signature 0000
PCI: 05:00.0 init
CBFS: Could not find file pci10ec,8168.rom
In cbfs, rom address for PCI: 05:00.0 = 00000000
On card, rom address for PCI: 05:00.0 = fc300000
Incorrect Expansion ROM Header Signature 0000
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:18.0: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 3 resources
PCI: 01:05.0: enabled 1, 5 resources
PCI: 00:02.0: enabled 0, 0 resources
PCI: 00:03.0: enabled 0, 0 resources
PCI: 00:04.0: enabled 1, 3 resources
PCI: 00:05.0: enabled 1, 3 resources
PCI: 00:06.0: enabled 1, 3 resources
PCI: 00:07.0: enabled 1, 3 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:12.0: enabled 1, 6 resources
PCI: 00:13.0: enabled 1, 1 resources
PCI: 00:13.1: enabled 1, 1 resources
PCI: 00:13.2: enabled 1, 1 resources
PCI: 00:13.3: enabled 1, 1 resources
PCI: 00:13.4: enabled 1, 1 resources
PCI: 00:13.5: enabled 1, 1 resources
PCI: 00:14.0: enabled 1, 3 resources
I2C: 01:50: enabled 1, 0 resources
I2C: 01:51: enabled 1, 0 resources
I2C: 01:52: enabled 1, 0 resources
I2C: 01:53: enabled 1, 0 resources
PCI: 00:14.1: enabled 1, 5 resources
PCI: 00:14.2: enabled 1, 1 resources
PCI: 00:14.3: enabled 1, 4 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 3 resources
PNP: 002e.2: enabled 1, 2 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.5: enabled 1, 4 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 1, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PNP: 002e.b: enabled 1, 2 resources
PNP: 002e.c: enabled 0, 0 resources
PCI: 00:14.4: enabled 1, 3 resources
PCI: 00:14.5: enabled 1, 1 resources
PCI: 00:14.6: enabled 1, 1 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 1 resources
PCI: 01:05.2: enabled 1, 1 resources
PCI: 04:00.0: enabled 1, 3 resources
PCI: 05:00.0: enabled 1, 3 resources
Initializing CBMEM area to 0x1bff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 0x1bff0200...ok
High Tables Base is 1bff0000.
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0x1bff0400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f0510
Adding CBMEM entry as no. 3
Wrote the mp table end at: 1bff1410 - 1bff1510
MP table: 272 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 1bff2400...
ACPI: * HPET
ACPI: added table 1/32 Length now 40
ACPI: * MADT
ACPI: added table 2/32 Length now 44
ACPI: * SSDT
processor_brand=Mobile AMD Sempron(tm) Processor 2100+
Pstates Algorithm ...
No valid set of P-states
ACPI: added table 3/32 Length now 48
ACPI: * FACS
ACPI: * DSDT
ACPI: * DSDT @ 1bff2760 Length 27ef
ACPI: * FADT
pm_base: 0x0800
ACPI: added table 4/32 Length now 52
ACPI: done.
ACPI tables: 11331 bytes.
Multiboot Information structure has been written.
Adding CBMEM entry as no. 5
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518 checksum 3df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x1bffe000
rom_table_end = 0x1bffe000
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x1bffe000 to 0x1c000000
Adding high table area
uma_memory_base=0x1c000000, uma_memory_size=0x4000000
Wrote coreboot table at: 1bffe000 - 1bffe1f4 checksum 233a
coreboot table: 500 bytes.
0. FREE SPACE 1c000000 00000000
1. GDT 1bff0200 00000200
2. IRQ TABLE 1bff0400 00001000
3. SMP TABLE 1bff1400 00001000
4. ACPI 1bff2400 0000bc00
5. COREBOOT 1bffe000 00002000
Got a payload
Loading segment from rom address 0xfff27d38
data (compression=1)
New segment dstaddr 0xf0000 memsize 0x10000 srcaddr 0xfff27d70 filesize 0x77b1
(cleaned up) New segment addr 0xf0000 size 0x10000 offset 0xfff27d70 filesize 0x77b1
Loading segment from rom address 0xfff27d54
Entry Point 0x000fc26b
Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x00000000000077b1
Post relocation: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x00000000000077b1
using LZMA
Jumping to boot code at fc26b
Start bios (version pre-0.4.3-20090925_172613-coresystems)
init ivt
init bda
init pic
init timer
tsc calibrate start=4286803442 end=4288521248 diff=1717806
CPU Mhz=1000
math cp init
Find memory size
Attempting to find coreboot table
Found coreboot table forwarder.
Now attempting to find coreboot memory map
Found mainboard KONTRON KT690
Found CBFS header at 0xfffbffe0
Ram Size=0x1bff0000
Found 1 cpu(s)
malloc setup
init PMM
init PNPBIOS table
Scan for VGA option rom
Attempting to init PCI bdf 01:05.0 (dev/ven 791f1002)
Searching CBFS for prefix pci1002,791f.rom
Found CBFS file pci1002,791f.rom
Copying data 65536@0xfff00038 to 196608@0x000c0000
Checking rom 0x000c0000 (sig aa55 size 109)
Running option rom at c000:0003
fail handle_15XX:294(86):
a=01284e08 b=00000080 c=00000000 d=0000c000 ds=c000 es=f000 ss=0000
si=0000ac14 di=0000b19e bp=00000000 sp=00007a56 cs=c000 ip=2d0e f=0046
fail handle_15XX:294(86):
a=00004e08 b=00000000 c=0000a491 d=00000080 ds=c000 es=f000 ss=0000
si=0000ac14 di=0000b19e bp=00007a4a sp=00007a54 cs=c000 ip=2c1b f=0046
Searching CBFS for prefix vgaroms/
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Turning on vga console
Welcome to coreboot(R) on Kontron KT690
init keyboard
i8042 ctr old=0 new=20
Got ps2 nak (status=51); continuing
ps2_recvbyte timeout
keyboard command 2ff failed
init lpt
Found 1 lpt ports
init serial
Found 2 serial ports
init mouse
Relocating coreboot bios tables
Copying PIR from 0x1bff0400 to 0x000fdcd0
Copying MPTABLE from 0x1bff1400/1bff1410 to 0x000fdbc0
Copying ACPI RSDP from 0x1bff2400 to 0x000fdba0
init SMBIOS tables
SMBIOS ptr=0x000fdb80 table=0x1bfef800
init boot device ordering
init hard drives
ATA controller 0 at 4020/4040 (dev 90 prog_if 8f)
ATA controller 1 at 4028/4044 (dev 90 prog_if 8f)
ATA controller 2 at 1f0/3f0 (dev a1 prog_if 8a)
ATA controller 3 at 170/370 (dev a1 prog_if 8a)
powerup iobase=4020 st=7f
powerup iobase=4020 st=7f
ata_detect ataid=0 sc=7f sn=7f dh=7f
powerup iobase=4020 st=7f
powerup iobase=4020 st=7f
ata_detect ataid=1 sc=7f sn=7f dh=7f
powerup iobase=4028 st=7f
powerup iobase=4028 st=7f
ata_detect ataid=2 sc=7f sn=7f dh=7f
powerup iobase=4028 st=7f
powerup iobase=4028 st=7f
ata_detect ataid=3 sc=7f sn=7f dh=7f
powerup iobase=1f0 st=50
powerup iobase=1f0 st=50
ata_detect ataid=4 sc=55 sn=aa dh=a0
ata_reset driveid=1
ata_reset exit status=50
send_cmd : read error (status=51 err=04)
Identify w0=45a w2=37c8
ata2-0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
ata2-0: IC35L060AVER07-0 ATA-5 Hard-Disk (58644 MiBytes)
ata_detect resetresult=403b
powerup iobase=1f0 st=50
powerup iobase=1f0 st=0
ata_detect ataid=5 sc=55 sn=aa dh=b0
Identify w0=85c0 w2=0
Mapping cd driveid 2 to 0
ata2-1: PIONEER DVD-RW DVR-111D ATAPI-5 DVD/CDROM
ata_detect resetresult=6d00
powerup IDE floating
powerup IDE floating
ata_detect ataid=6 sc=ff sn=ff dh=ff
powerup IDE floating
powerup IDE floating
ata_detect ataid=7 sc=ff sn=ff dh=ff
Searching CBFS for prefix floppyimg/
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Scan for option roms
Attempting to init PCI bdf 00:00.0 (dev/ven 79101002)
Searching CBFS for prefix pci1002,7910.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:01.0 (dev/ven 79121002)
Searching CBFS for prefix pci1002,7912.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:01.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:04.0 (dev/ven 79141002)
Searching CBFS for prefix pci1002,7914.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:04.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:05.0 (dev/ven 79151002)
Searching CBFS for prefix pci1002,7915.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:05.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:06.0 (dev/ven 79161002)
Searching CBFS for prefix pci1002,7916.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:06.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:07.0 (dev/ven 79171002)
Searching CBFS for prefix pci1002,7917.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:07.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:13.0 (dev/ven 43871002)
Searching CBFS for prefix pci1002,4387.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:13.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.1 (dev/ven 43881002)
Searching CBFS for prefix pci1002,4388.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:13.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.2 (dev/ven 43891002)
Searching CBFS for prefix pci1002,4389.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:13.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.3 (dev/ven 438a1002)
Searching CBFS for prefix pci1002,438a.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:13.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.4 (dev/ven 438b1002)
Searching CBFS for prefix pci1002,438b.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:13.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.5 (dev/ven 43861002)
Searching CBFS for prefix pci1002,4386.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:13.5
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.0 (dev/ven 43851002)
Searching CBFS for prefix pci1002,4385.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:14.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.2 (dev/ven 43831002)
Searching CBFS for prefix pci1002,4383.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:14.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.3 (dev/ven 438d1002)
Searching CBFS for prefix pci1002,438d.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:14.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.4 (dev/ven 43841002)
Searching CBFS for prefix pci1002,4384.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:14.4
Skipping non-normal pci device (type=81)
Attempting to init PCI bdf 00:18.0 (dev/ven 11001022)
Searching CBFS for prefix pci1022,1100.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:18.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.1 (dev/ven 11011022)
Searching CBFS for prefix pci1022,1101.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:18.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.2 (dev/ven 11021022)
Searching CBFS for prefix pci1022,1102.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:18.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.3 (dev/ven 11031022)
Searching CBFS for prefix pci1022,1103.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 00:18.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 01:05.2 (dev/ven 79191002)
Searching CBFS for prefix pci1002,7919.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 01:05.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 04:00.0 (dev/ven 816810ec)
Searching CBFS for prefix pci10ec,8168.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 04:00.0
Option rom sizing returned fc200001 fffe0000
Inspecting possible rom at 0xfc200000 (dv=816810ec bdf=400)
No option rom signature (got 0)
Attempting to init PCI bdf 05:00.0 (dev/ven 816810ec)
Searching CBFS for prefix pci10ec,8168.rom
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Attempting to map option rom on dev 05:00.0
Option rom sizing returned fc300001 fffe0000
Inspecting possible rom at 0xfc300000 (dv=816810ec bdf=500)
No option rom signature (got 0)
Searching CBFS for prefix genroms/
Found CBFS file pci1002,791f.rom
Found CBFS file normal/payload
Found CBFS file normal/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file
Press F12 for boot menu.
Mapping hd driveid 1 to 0
finalize PMM
malloc finalize
zone 0: 00007c00-00060000 used=0 (0%)
zone 1: 000a0000-000a0000 used=0 (0%)
zone 2: 000fd500-000fdd00 used=384 (18%)
zone 3: 00100000-1bfe0000 used=0 (0%)
zone 4: 1bfe0000-1bff0000 used=2048 (3%)
Returned 61440 bytes of ZoneHigh
e820 map has 5 items:
0: 0000000000000000 - 000000000009f400 = 1
1: 000000000009f400 - 00000000000a0000 = 2
2: 00000000000f0000 - 0000000000100000 = 2
3: 0000000000100000 - 000000001bfef000 = 1
4: 000000001bfef000 - 0000000020000000 = 2
Jump to int19
enter handle_19:
NULL
Booting from DVD/CDROM...
atapi_is_ready (driveid=2)
send_atapi_cmd : read error (status=51 err=60)
Device reports MEDIUM NOT PRESENT
atapi_is_ready returned -1
Boot failed: Could not read from CDROM (code 0003)
enter handle_18:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
ata_reset driveid=1
ata_reset exit status=50
enter handle_12:
a=00000000 b=00000000 c=00000000 d=00000080 ds=0000 es=0000 ss=0000
si=00158116 di=0002c684 bp=00001ff0 sp=00001ff4 cs=0000 ip=8a03 f=0297
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=0002c70c d=0002c781 ds=0000 es=0000 ss=0000
si=00067fc4 di=00000081 bp=00001ff0 sp=00001ff4 cs=0000 ip=88b5 f=0246
fail handle_legacy_disk:801(1):
a=00000800 b=00000000 c=0002c70c d=0002c781 ds=0000 es=0000 ss=0000
si=00067fc4 di=00000081 bp=00001ff0 sp=00001ff4 cs=0000 ip=88eb f=0246
fail handle_15XX:294(86):
a=000000c0 b=00000000 c=0002c700 d=00000001 ds=0000 es=0000 ss=0000
si=00067fc4 di=00000000 bp=00001ff0 sp=00001ff4 cs=0000 ip=8ab8 f=0246
fail handle_legacy_disk:801(1):
a=00000000 b=00009000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000
si=00373320 di=0009a000 bp=00001ff0 sp=00001ff4 cs=0000 ip=82c5 f=0246
fail handle_15XX:294(86):
a=0000ec00 b=00000002 c=00000000 d=00008fb4 ds=9000 es=9000 ss=9000
si=00000258 di=00003618 bp=00001ff0 sp=00008fd0 cs=9000 ip=1164 f=0246
stub handle_16XX:297:
a=00000305 b=00000000 c=00003c00 d=00003eff ds=9000 es=9000 ss=9000
si=00000258 di=00003618 bp=00001ff0 sp=00008fd0 cs=9000 ip=1175 f=0246
fail handle_15XX:294(86):
a=0000e980 b=00000000 c=00000000 d=47534943 ds=9000 es=9000 ss=9000
si=00000258 di=00003618 bp=00001ff0 sp=00008fd0 cs=9000 ip=1191 f=0212
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000081 d=00000081 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910081 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000082 d=00000082 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910082 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000083 d=00000083 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910083 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000084 d=00000084 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910084 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000085 d=00000085 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910085 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000086 d=00000086 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910086 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000087 d=00000087 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910087 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000088 d=00000088 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910088 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=00000089 d=00000089 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=11910089 ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=0000008a d=0000008a ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=1191008a ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=0000008b d=0000008b ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=1191008b ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=0000008c d=0000008c ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=1191008c ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=0000008d d=0000008d ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=1191008d ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=0000008e d=0000008e ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=1191008e ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
fail handle_legacy_disk:801(1):
a=00004100 b=000055aa c=0000008f d=0000008f ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=0ec8 f=0247
fail handle_legacy_disk:801(1):
a=00000201 b=00004400 c=00000001 d=1191008f ds=9000 es=9000 ss=9000
si=00008fb4 di=00008fb4 bp=00004400 sp=00008f2c cs=9000 ip=1018 f=0287
Initializing cgroup subsys cpuset
Initializing cgroup subsys cpu
Linux version 2.6.27.29-0.1-default (geeko@buildhost) (gcc version 4.3.2 [gcc-4_3-branch revision 141291] (SUSE Linux) ) #1 SMP 2009-08-15 17:53:59 +0200
Command line: root=/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2 resume=/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part1 splash=silent vga=0x345 console=ttyS0,115200n8 console=tty0
KERNEL supported cpus:
Intel GenuineIntel
AMD AuthenticAMD
Centaur CentaurHauls
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009f400 (usable)
BIOS-e820: 000000000009f400 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000001bfef000 (usable)
BIOS-e820: 000000001bfef000 - 0000000020000000 (reserved)
DMI 2.4 present.
last_pfn = 0x1bfef max_arch_pfn = 0x100000000
x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
init_memory_mapping
last_map_addr: 1bfef000 end: 1bfef000
RAMDISK: 1ba33000 - 1bfde491
ACPI: RSDP 000FDBA0, 0014 (r0 CORE )
ACPI: RSDT 1BFF2424, 0034 (r1 CORE COREBOOT 0 CORE 0)
ACPI: HPET 1BFF24C8, 0038 (r1 CORE COREBOOT 0 CORE 0)
ACPI: APIC 1BFF2500, 0054 (r1 CORE COREBOOT 0 CORE 0)
ACPI: SSDT 1BFF2554, 01CC (r2 CORE DYNADATA 2A CORE 2A)
ACPI: FACP 1BFF4F4F, 00F4 (r1 CORE COREBOOT 0 CORE 0)
ACPI: DSDT 1BFF2760, 27EF (r2 COREv2 COREBOOT 10001 INTL 20090730)
ACPI: FACS 1BFF2720, 0040
Scanning NUMA topology in Northbridge 24
No NUMA configuration found
Faking a node at 0000000000000000-000000001bfef000
Bootmem setup node 0 0000000000000000-000000001bfef000
NODE_DATA [0000000000009000 - 0000000000020fff]
bootmap [0000000000021000 - 00000000000247ff] pages 4
(6 early reservations) ==> bootmem [0000000000 - 001bfef000]
#0 [0000000000 - 0000001000] BIOS data page ==> [0000000000 - 0000001000]
#1 [0000006000 - 0000008000] TRAMPOLINE ==> [0000006000 - 0000008000]
#2 [0000200000 - 0000bcc8b8] TEXT DATA BSS ==> [0000200000 - 0000bcc8b8]
#3 [001ba33000 - 001bfde491] RAMDISK ==> [001ba33000 - 001bfde491]
#4 [000009f400 - 0000100000] BIOS reserved ==> [000009f400 - 0000100000]
#5 [0000008000 - 0000009000] PGTABLE ==> [0000008000 - 0000009000]
found SMP MP-table at [ffff8800000fdbc0] 000fdbc0
Zone PFN ranges:
DMA 0x00000000 -> 0x00001000
DMA32 0x00001000 -> 0x00100000
Normal 0x00100000 -> 0x00100000
Movable zone start PFN for each node
early_node_map[2] active PFN ranges
0: 0x00000000 -> 0x0000009f
0: 0x00000100 -> 0x0001bfef
ACPI: PM-Timer IO Port: 0x818
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
IOAPIC[0]: apic_id 2, version 0, address 0xfec00000, GSI 0-23
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
ACPI: HPET id: 0x102282a0 base: 0xfed00000
Using ACPI (MADT) for SMP configuration information
SMP: Allowing 1 CPUs, 0 hotplug CPUs
PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000
PM: Registered nosave memory: 00000000000f0000 - 0000000000100000
Allocating PCI resources starting at 30000000 (gap: 20000000:e0000000)
PERCPU: Allocating 61472 bytes of per cpu data
Built 1 zonelists in Node order, mobility grouping on. Total pages: 110172
Policy zone: DMA32
Kernel command line: root=/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2 resume=/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part1 splash=silent vga=0x345 console=ttyS0,115200n8 console=tty0
bootsplash: silent mode.
Initializing CPU#0
PID hash table entries: 2048 (order: 11, 16384 bytes)
TSC: PIT calibration confirmed by PMTIMER.
TSC: using PIT calibration value
Detected 1000.021 MHz processor.
Console: colour dummy device 80x25
console [tty0] enabled
console [ttyS0] enabled
Checking aperture...
No AGP bridge found
Node 0: aperture @ f8000000 size 64 MB
Memory: 433832k/458684k available (2703k kernel code, 24464k reserved, 3168k data, 792k init)
Calibrating delay loop (skipped), value calculated using timer frequency.. 2000.04 BogoMIPS (lpj=4000084)
kdb version 4.4 by Keith Owens, Scott Lurndal. Copyright SGI, All Rights Reserved
kdb_cmd[0]: defcmd archkdb "" "First line arch debugging"
kdb_cmd[7]: defcmd archkdbcpu "" "archkdb with only tasks on cpus"
kdb_cmd[14]: defcmd archkdbshort "" "archkdb with less detailed backtrace"
kdb_cmd[21]: defcmd archkdbcommon "" "Common arch debugging"
Security Framework initialized
AppArmor: AppArmor initialized
Dentry cache hash table entries: 65536 (order: 7, 524288 bytes)
Inode-cache hash table entries: 32768 (order: 6, 262144 bytes)
Mount-cache hash table entries: 256
Initializing cgroup subsys ns
Initializing cgroup subsys cpuacct
Initializing cgroup subsys memory
Initializing cgroup subsys devices
Initializing cgroup subsys freezer
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 256K (64 bytes/line)
CPU 0/0 -> Node 0
using C1E aware idle routine
SMP alternatives: switching to UP code
Freeing SMP alternatives: 25k freed
ACPI: Core revision 20080609
ACPI: Checking initramfs for custom DSDT
Parsing all Control Methods:
Table [DSDT](id 0001) - 512 Objects with 49 Devices 117 Methods 14 Regions
Parsing all Control Methods:
Table [SSDT](id 0002) - 14 Objects with 0 Devices 1 Methods 0 Regions
tbxface-0596 [00] tb_load_namespace : ACPI Tables successfully acquired
evxfevnt-0079 [00] enable : System is already in ACPI mode
Setting APIC routing to flat
..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
CPU0: Mobile AMD Sempron(tm) Processor 2100+ stepping 02
Using local APIC timer interrupts.
Detected 12.500 MHz APIC timer.
Brought up 1 CPUs
Total of 1 processors activated (2000.04 BogoMIPS).
net_namespace: 1936 bytes
NET: Registered protocol family 16
TOM: 0000000020000000 aka 512M
TOM2: 0000000000000000 aka 0M
ACPI: bus type pci registered
PCI: Using configuration type 1 for base access
perfmon: version 2.82
perfmon: CPU hotplug support enabled
evgpeblk-0957 [00] ev_create_gpe_block : GPE 00 to 1F [_GPE] 4 regs on int 0x9
Completing Region/Field/Buffer/Package initialization:........................................................................
Initialized 11/14 Regions 0/0 Fields 12/12 Buffers 49/49 Packages (535 nodes)
Initializing Device/Processor/Thermal objects by executing _INI methods:...
Executed 3 _INI methods requiring 1 _STA executions (examined 53 objects)
evgpeblk-1054 [00] ev_initialize_gpe_bloc: Found 3 Wake, Enabled 16 Runtime GPEs in this block
ACPI: Interpreter enabled
ACPI: (supports S0 S1 S2 S3 S4 S5)
ACPI: Using IOAPIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (0000:00)
pci 0000:00:04.0: PME# supported from D0 D3hot D3cold
pci 0000:00:04.0: PME# disabled
pci 0000:00:05.0: PME# supported from D0 D3hot D3cold
pci 0000:00:05.0: PME# disabled
pci 0000:00:06.0: PME# supported from D0 D3hot D3cold
pci 0000:00:06.0: PME# disabled
pci 0000:00:07.0: PME# supported from D0 D3hot D3cold
pci 0000:00:07.0: PME# disabled
pci 0000:00:12.0: set SATA to AHCI mode
pci 0000:00:13.5: PME# supported from D0 D1 D2 D3hot
pci 0000:00:13.5: PME# disabled
pci 0000:00:14.2: PME# supported from D0 D3hot D3cold
pci 0000:00:14.2: PME# disabled
pci 0000:04:00.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:04:00.0: PME# disabled
Pre-1.1 PCIe device detected, disable ASPM for 0000:00:06.0. It can be enabled forcedly with 'pcie_aspm=force'
pci 0000:05:00.0: PME# supported from D1 D2 D3hot D3cold
pci 0000:05:00.0: PME# disabled
Pre-1.1 PCIe device detected, disable ASPM for 0000:00:07.0. It can be enabled forcedly with 'pcie_aspm=force'
pci 0000:00:14.4: transparent bridge
ACPI: PCI Interrupt Link [INTA] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
ACPI: PCI Interrupt Link [INTB] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0, disabled.
ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
ACPI: Power Resource [PFN0] (on)
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
ACPI: bus type pnp registered
pnp: PnP ACPI: found 6 devices
ACPI: ACPI bus type pnp unregistered
PCI: Using ACPI for IRQ routing
pci 0000:00:00.0: BAR 3: can't allocate resource
hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
hpet0: 4 32-bit timers, 14318180 Hz
AppArmor: AppArmor Filesystem Enabled
ACPI: RTC can wake from S4
pci 0000:00:01.0: PCI bridge, secondary bus 0000:01
pci 0000:00:01.0: IO window: 0x1000-0x1fff
pci 0000:00:01.0: MEM window: 0xfc000000-0xfc1fffff
pci 0000:00:01.0: PREFETCH window: 0x000000f0000000-0x000000f7ffffff
pci 0000:00:04.0: PCI bridge, secondary bus 0000:02
pci 0000:00:04.0: IO window: disabled
pci 0000:00:04.0: MEM window: disabled
pci 0000:00:04.0: PREFETCH window: disabled
pci 0000:00:05.0: PCI bridge, secondary bus 0000:03
pci 0000:00:05.0: IO window: disabled
pci 0000:00:05.0: MEM window: disabled
pci 0000:00:05.0: PREFETCH window: disabled
pci 0000:00:06.0: PCI bridge, secondary bus 0000:04
pci 0000:00:06.0: IO window: 0x2000-0x2fff
pci 0000:00:06.0: MEM window: 0xfc200000-0xfc2fffff
pci 0000:00:06.0: PREFETCH window: disabled
pci 0000:00:07.0: PCI bridge, secondary bus 0000:05
pci 0000:00:07.0: IO window: 0x3000-0x3fff
pci 0000:00:07.0: MEM window: 0xfc300000-0xfc3fffff
pci 0000:00:07.0: PREFETCH window: disabled
pci 0000:00:14.4: PCI bridge, secondary bus 0000:06
pci 0000:00:14.4: IO window: disabled
pci 0000:00:14.4: MEM window: disabled
pci 0000:00:14.4: PREFETCH window: disabled
bus: 00 index 0 io port: [0, ffff]
bus: 00 index 1 mmio: [0, ffffffffffffffff]
bus: 01 index 0 io port: [1000, 1fff]
bus: 01 index 1 mmio: [fc000000, fc1fffff]
bus: 01 index 2 mmio: [f0000000, f7ffffff]
bus: 01 index 3 mmio: [0, 0]
bus: 02 index 0 mmio: [0, 0]
bus: 02 index 1 mmio: [0, 0]
bus: 02 index 2 mmio: [0, 0]
bus: 02 index 3 mmio: [0, 0]
bus: 03 index 0 mmio: [0, 0]
bus: 03 index 1 mmio: [0, 0]
bus: 03 index 2 mmio: [0, 0]
bus: 03 index 3 mmio: [0, 0]
bus: 04 index 0 io port: [2000, 2fff]
bus: 04 index 1 mmio: [fc200000, fc2fffff]
bus: 04 index 2 mmio: [0, 0]
bus: 04 index 3 mmio: [0, 0]
bus: 05 index 0 io port: [3000, 3fff]
bus: 05 index 1 mmio: [fc300000, fc3fffff]
bus: 05 index 2 mmio: [0, 0]
bus: 05 index 3 mmio: [0, 0]
bus: 06 index 0 mmio: [0, 0]
bus: 06 index 1 mmio: [0, 0]
bus: 06 index 2 mmio: [0, 0]
bus: 06 index 3 io port: [0, ffff]
bus: 06 index 4 mmio: [0, ffffffffffffffff]
NET: Registered protocol family 2
IP route cache hash table entries: 4096 (order: 3, 32768 bytes)
TCP established hash table entries: 16384 (order: 6, 262144 bytes)
TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
TCP: Hash tables configured (established 16384 bind 16384)
TCP reno registered
NET: Registered protocol family 1
Unpacking initramfs... done
Freeing initrd memory: 5805k freed
audit: initializing netlink socket (disabled)
type=2000 audit(1237559985.600:1): initialized
HugeTLB registered 2 MB page size, pre-allocated 0 pages
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
msgmni has been set to 214
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
perfmon: added sampling format default
pcieport-driver 0000:00:04.0: found MSI capability
pcieport-driver 0000:00:05.0: found MSI capability
pcieport-driver 0000:00:06.0: found MSI capability
pcieport-driver 0000:00:07.0: found MSI capability
vesafb: framebuffer at 0xf0000000, mapped to 0xffffc20000180000, using 11550k, total 16384k
vesafb: mode is 1400x1050x16, linelength=2816, pages=4
vesafb: scrolling: redraw
vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0
bootsplash 3.1.6-2004/03/31: looking for picture...
bootsplash: silentjpeg size 113987 bytes
bootsplash: ...found (1400x1050, 45904 bytes, v3).
Console: switching to colour frame buffer device 171x61
fb0: VESA VGA frame buffer device
Non-volatile memory driver v1.2
Linux agpgart interface v0.103
Serial: 8250/16550 driver8 ports, IRQ sharing disabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
PNP: No PS/2 controller found. Probing ports directly.
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mice: PS/2 mouse device common for all mice
cpuidle: using governor ladder
cpuidle: using governor menu
TCP cubic registered
registered taskstats version 1
Freeing unused kernel memory: 792k freed
Write protecting the kernel read-only data: 4940k
processor ACPI_CPU:00: registered as cooling_device0
ACPI: Processor [CPU0] (supports 8 throttling states)
thermal LNXTHERM:01: registered as thermal_zone0
ACPI: Thermal Zone [TZ00] (40 C)
ACPI: No dock devices found.
SCSI subsystem initialized
ahci 0000:00:12.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
ahci 0000:00:12.0: controller can't do 64bit DMA, forcing 32bit
ahci 0000:00:12.0: AHCI 0001.0100 32 slots 4 ports 3 Gbps 0xf impl SATA mode
ahci 0000:00:12.0: flags: ncq sntf ilck pm led clo pmp pio slum part
scsi0 : ahci
scsi1 : ahci
scsi2 : ahci
scsi3 : ahci
ata1: SATA max UDMA/133 abar m1024@0xfc409000 port 0xfc409100 irq 22
ata2: SATA max UDMA/133 abar m1024@0xfc409000 port 0xfc409180 irq 22
ata3: SATA max UDMA/133 abar m1024@0xfc409000 port 0xfc409200 irq 22
ata4: SATA max UDMA/133 abar m1024@0xfc409000 port 0xfc409280 irq 22
ata1: SATA link down (SStatus 0 SControl 300)
ata2: SATA link down (SStatus 0 SControl 300)
ata3: SATA link down (SStatus 0 SControl 300)
ata4: SATA link down (SStatus 0 SControl 300)
pata_atiixp 0000:00:14.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16
scsi4 : pata_atiixp
scsi5 : pata_atiixp
ata5: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x4010 irq 14
ata6: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x4018 irq 15
ata5.00: ATA-5: IC35L060AVER07-0, ER6OA46A, max UDMA/100
ata5.00: 120103200 sectors, multi 0: LBA
ata5.01: ATAPI: PIONEER DVD-RW DVR-111D, 1.02, max UDMA/66
ata5.00: configured for UDMA/100
ata5.01: configured for UDMA/66
isa bounce pool size: 16 pages
scsi 4:0:0:0: Direct-Access ATA IC35L060AVER07-0 ER6O PQ: 0 ANSI: 5
scsi 4:0:1:0: CD-ROM PIONEER DVD-RW DVR-111D 1.02 PQ: 0 ANSI: 5
Uniform Multi-Platform E-IDE driver
fan PNP0C0B:00: registered as cooling_device1
ACPI: Fan [FAN0] (on)
BIOS EDD facility v0.16 2004-Jun-25, 1 devices found
udevd version 128 started
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
ohci_hcd 0000:00:13.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
ohci_hcd 0000:00:13.0: OHCI Host Controller
ohci_hcd 0000:00:13.0: new USB bus registered, assigned bus number 1
ohci_hcd 0000:00:13.0: irq 16, io mem 0xfc404000
Warning! ehci_hcd should always be loaded before uhci_hcd and ohci_hcd, not after
sd 4:0:0:0: [sda] 120103200 512-byte hardware sectors: (61.4 GB/57.2 GiB)
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
sd 4:0:0:0: [sda] Write Protect is off
sd 4:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
sd 4:0:0:0: [sda] 120103200 512-byte hardware sectors: (61.4 GB/57.2 GiB)
sd 4:0:0:0: [sda] Write Protect is off
sd 4:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
sda: sda1 sda2 sda3
sd 4:0:0:0: [sda] Attached SCSI disk
usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: OHCI Host Controller
usb usb1: Manufacturer: Linux 2.6.27.29-0.1-default ohci_hcd
usb usb1: SerialNumber: 0000:00:13.0
ohci_hcd 0000:00:13.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
ohci_hcd 0000:00:13.1: OHCI Host Controller
ohci_hcd 0000:00:13.1: new USB bus registered, assigned bus number 2
ohci_hcd 0000:00:13.1: irq 17, io mem 0xfc405000
usb usb2: configuration #1 chosen from 1 choice
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb2: Product: OHCI Host Controller
usb usb2: Manufacturer: Linux 2.6.27.29-0.1-default ohci_hcd
usb usb2: SerialNumber: 0000:00:13.1
ohci_hcd 0000:00:13.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
ohci_hcd 0000:00:13.2: OHCI Host Controller
ohci_hcd 0000:00:13.2: new USB bus registered, assigned bus number 3
ohci_hcd 0000:00:13.2: irq 18, io mem 0xfc406000
usb usb3: configuration #1 chosen from 1 choice
hub 3-0:1.0: USB hub found
hub 3-0:1.0: 2 ports detected
usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb3: Product: OHCI Host Controller
usb usb3: Manufacturer: Linux 2.6.27.29-0.1-default ohci_hcd
usb usb3: SerialNumber: 0000:00:13.2
ohci_hcd 0000:00:13.3: PCI INT B -> GSI 17 (level, low) -> IRQ 17
ohci_hcd 0000:00:13.3: OHCI Host Controller
ohci_hcd 0000:00:13.3: new USB bus registered, assigned bus number 4
ohci_hcd 0000:00:13.3: irq 17, io mem 0xfc407000
usb usb4: configuration #1 chosen from 1 choice
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 2 ports detected
usb 3-1: new low speed USB device using ohci_hcd and address 2
usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb4: Product: OHCI Host Controller
usb usb4: Manufacturer: Linux 2.6.27.29-0.1-default ohci_hcd
usb usb4: SerialNumber: 0000:00:13.3
ohci_hcd 0000:00:13.4: PCI INT C -> GSI 18 (level, low) -> IRQ 18
ohci_hcd 0000:00:13.4: OHCI Host Controller
ohci_hcd 0000:00:13.4: new USB bus registered, assigned bus number 5
ohci_hcd 0000:00:13.4: irq 18, io mem 0xfc408000
usb usb5: configuration #1 chosen from 1 choice
hub 5-0:1.0: USB hub found
hub 5-0:1.0: 2 ports detected
usb 3-1: configuration #1 chosen from 1 choice
usb 3-1: New USB device found, idVendor=046d, idProduct=c016
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 3-1: Product: Optical USB Mouse
usb 3-1: Manufacturer: Logitech
usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb5: Product: OHCI Host Controller
usb usb5: Manufacturer: Linux 2.6.27.29-0.1-default ohci_hcd
usb usb5: SerialNumber: 0000:00:13.4
ehci_hcd 0000:00:13.5: PCI INT D -> GSI 19 (level, low) -> IRQ 19
ehci_hcd 0000:00:13.5: EHCI Host Controller
ehci_hcd 0000:00:13.5: new USB bus registered, assigned bus number 6
ehci_hcd 0000:00:13.5: applying AMD SB600/SB700 USB freeze workaround
ehci_hcd 0000:00:13.5: debug port 1
ehci_hcd 0000:00:13.5: irq 19, io mem 0xfc409400
ehci_hcd 0000:00:13.5: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004
usb usb6: configuration #1 chosen from 1 choice
hub 6-0:1.0: USB hub found
hub 6-0:1.0: 10 ports detected
usb 3-1: USB disconnect, address 2
usb usb6: New USB device found, idVendor=1d6b, idProduct=0002
usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb6: Product: EHCI Host Controller
usb usb6: Manufacturer: Linux 2.6.27.29-0.1-default ehci_hcd
usb usb6: SerialNumber: 0000:00:13.5
usbcore: registered new interface driver hiddev
usb 3-1: new low speed USB device using ohci_hcd and address 3
usb 3-1: configuration #1 chosen from 1 choice
usb 3-1: New USB device found, idVendor=046d, idProduct=c016
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 3-1: Product: Optical USB Mouse
usb 3-1: Manufacturer: Logitech
usb 5-2: new low speed USB device using ohci_hcd and address 2
usb 5-2: configuration #1 chosen from 1 choice
usb 5-2: New USB device found, idVendor=1267, idProduct=0103
usb 5-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
input: Logitech Optical USB Mouse as /devices/pci0000:00/0000:00:13.2/usb3/3-1/3-1:1.0/input/input0
input,hidraw0: USB HID v1.10 Mouse [Logitech Optical USB Mouse] on usb-0000:00:13.2-1
input: HID 1267:0103 as /devices/pci0000:00/0000:00:13.4/usb5/5-2/5-2:1.0/input/input1
input,hidraw1: USB HID v1.10 Keyboard [HID 1267:0103] on usb-0000:00:13.4-2
input: HID 1267:0103 as /devices/pci0000:00/0000:00:13.4/usb5/5-2/5-2:1.1/input/input2
input,hidraw2: USB HID v1.10 Device [HID 1267:0103] on usb-0000:00:13.4-2
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
Boot logging started on /dev/tty1(/dev/console) at Fri Mar 20 14:39:52 2009
Trying manual resume from /dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part1
Invoking userspace resume from /dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part1
resume: libgcrypt version: 1.4.1
Trying manual resume from /dev/disk/by-id/ata-IC35L060AVER07-0_SPM: Starting manual resume from disk
ZPTZ204546-part1
Invoking in-kernel resume from /dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part1
Waiting for device /dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2 to appear: ok
fsck 1.41.1 (01-Sep-2008)
[/sbin/fsck.ext3 (1) -- /] fsck.ext3 -a -C0 /dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2
/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2: recovering journal
/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2: Clearing orphaned inode 1255941 (uid=0, gid=0, mode=0100600, size=217016)
/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2: clean, 150917/1313280 files, 1002490/5242880 blocks
fsck succeeded. Mounting root device read-write.
Mounting root /dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part2
kjournald starting. Commit interval 5 seconds
EXT3 FS on sda2, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
Boot logging started on /dev/tty1(/dev/console (deleted)) at Fri Mar 20 15:39:59 2009
done
Starting udevd: udevd version 128 started
done
Loading drivers, configuring devices: r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
vendor=1002 device=7916
r8169 0000:04:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
eth0: RTL8168b/8111b at 0xffffc20000cd8000, 00:e0:f4:1a:22:a9, XID 38500000 IRQ 4347
r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
vendor=1002 device=7917
r8169 0000:05:00.0: PCI INT A -> GSI 19 (level, low) -> IRQ 19
eth1: RTL8168b/8111b at 0xffffc20000cda000, 00:e0:f4:1a:22:aa, XID 38500000 IRQ 4346
pci_hotplug: PCI Hot Plug PCI Core version: 0.5
shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
input: Power Button (FF) as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
ACPI: Power Button (FF) [PWRF]
input: Power Button (CM) as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input4
ACPI: Power Button (CM) [PWRB]
HDA Intel 0000:00:14.2: PCI INT A -> GSI 16 (level, low) -> IRQ 16
hda_codec: Unknown model for ALC883, trying auto-probe from BIOS...
vendor=1002 device=7912
HDA Intel 0000:01:05.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19
sd 4:0:0:0: Attached scsi generic sg0 type 0
scsi 4:0:1:0: Attached scsi generic sg1 type 5
ACPI: I/O resource piix4_smbus [0xb00-0xb07] conflicts with ACPI region SMB0 [0xb00-0xb0b]
ACPI: Device needs an ACPI driver
piix4_smbus 0000:00:14.0: SMBus Host Controller at 0xb00, revision 0
sr0: scsi3-mmc drive: 40x/40x writer cd/rw xa/form2 cdda tray
Uniform CD-ROM driver Revision: 3.20
input: PC Speaker as /devices/platform/pcspkr/input/input5
rtc_cmos 00:01: rtc core: registered rtc_cmos as rtc0
rtc0: alarms up to one day, hpet irqs
done
Loading required kernel modules
doneActivating swap-devices in /etc/fstab...
Adding 706820k swap on /dev/sda1. Priority:-1 extents:1 across:706820k
doneSetting up the hardware clockdone
Starting MD Raid unused
Activating device mapper...
device-mapper: uevent: version 1.0.3
device-mapper: ioctl: 4.14.0-ioctl (2008-04-23) initialised: dm-devel@redhat.com
done
Checking file systems...
fsck 1.41.1 (01-Sep-2008)
/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part3: recovering journal
/dev/disk/by-id/ata-IC35L060AVER07-0_SZPTZ204546-part3: clean, 10719/2400256 files, 242666/9592813 blocks
donedone
Mounting local file systems...
/proc on /proc type proc (rw)
sysfs on /sys type sysfs (rw)
debugfs on /sys/kernel/debug type debugfs (rw)
udev on /dev type tmpfs (rw)
loop: module loaded
devpts on /dev/pts type devpts (rw,mode=0620,gid=5)
kjournald starting. Commit interval 5 seconds
EXT3 FS on sda3, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
/dev/sda3 on /home type ext3 (rw,acl,user_xattr)
donefuse init (API version 7.9)
Loading fuse module done
Mounting fuse control filesystemdone
Creating /var/log/boot.msg
doneMounting securityfs on /sys/kernel/security done
Loading AppArmor profiles type=1505 audit(1237560009.972:2): operation="profile_load" name="/bin/ping" name2="default" pid=1629
type=1505 audit(1237560010.244:3): operation="profile_load" name="/sbin/klogd" name2="default" pid=1651
Activating remaining swap-devices in /etc/fstab...
donetype=1505 audit(1237560010.544:4): operation="profile_load" name="/sbin/syslog-ng" name2="default" pid=1685
type=1505 audit(1237560010.768:5): operation="profile_load" name="/sbin/syslogd" name2="default" pid=1707
type=1505 audit(1237560011.044:6): operation="profile_load" name="/usr/sbin/avahi-daemon" name2="default" pid=1728
Setting up hostname 'linux-klsv'done
Setting up loopback interface lo
lo IP address: 127.0.0.1/8
IP address: 127.0.0.2/8
done
type=1505 audit(1237560011.276:7): operation="profile_load" name="/usr/sbin/identd" name2="default" pid=1746
type=1505 audit(1237560011.512:8): operation="profile_load" name="/usr/sbin/mdnsd" name2="default" pid=1754
Setting current sysctl status from /etc/sysctl.conf
net.ipv4.icmp_echo_ignore_broadcasts = 1
net.ipv4.conf.all.rp_filter = 1
fs.inotify.max_user_watches = 65536
net.ipv4.conf.default.promote_secondaries = 1
net.ipv4.conf.all.promote_secondaries = 1
done
type=1505 audit(1237560011.956:9): operation="profile_load" name="/usr/sbin/nscd" name2="default" pid=1772
Enabling syn flood protectiondone
Disabling IP forwardingdone
done
type=1505 audit(1237560012.308:10): operation="profile_load" name="/usr/sbin/ntpd" name2="default" pid=1778
type=1505 audit(1237560012.476:11): operation="profile_load" name="/usr/sbin/traceroute" name2="default" pid=1797
done
System Boot Control: The system has been set up
Skipped features: boot.md boot.cycle
System Boot Control: Running /etc/init.d/boot.local
doneINIT: Entering runlevel: 5
Boot logging started on /dev/tty1(/dev/console) at Fri Mar 20 15:40:12 2009
Master Resource Control: previous runlevel: N, switching to runlevel: 5
Starting syslog servicesdone
Starting D-Bus daemondone
Starting acpid done
Loading CPUFreq modulespowernow-k8: Power state transitions not supported
r8169: eth0: link up
r8169: eth0: link up
NET: Registered protocol family 17
Initializing random number generatordone
(CPUFreq not supported)
Starting HAL daemondone
Setting up (localfs) network interfaces:
lo
lo IP address: 127.0.0.1/8
IP address: 127.0.0.2/8
lo
done eth0 device: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
eth0 Starting DHCP4 client.
eth0 IP address: 192.168.0.24/24
eth0
done eth1 device: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
No configuration found for eth1
eth1
unusedSetting up service (localfs) network . . . . . . . . . .done
Starting service kdmdone
Starting rpcbind done
Not starting NFS client services - no NFS found in /etc/fstab:unused
Loading console font lat9w-16.psfu -m trivial G0:loadable
doneLoading keymap assuming iso-8859-15 euro
Loading /usr/share/kbd/keymaps/i386/qwertz/de-latin1-nodeadkeys.map.gz
doneLoading compose table latin1.adddone
Start Unicode mode
doneStarting auditd done
Starting Avahi daemon done
Starting cupsddone
Starting irqbalance unused
Starting java.binfmt_misc done
Setting up (remotefs) network interfaces:
Setting up service (remotefs) network . . . . . . . . . .done
Starting Name Service Cache Daemondone
Starting mail service (Postfix)done
Starting CRON daemondone
Starting SSH daemondone
Starting smartd done
done
Master Resource Control: runlevel 5 has been reached
Skipped services in runlevel 5: nfs irq_balancer
Welcome to openSUSE 11.1 - Kernel 2.6.27.29-0.1-default (ttyS0).
linux-klsv login: