On Sep 26, 2009, at 2:41, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net
wrote:
On 25.09.2009 20:04, Myles Watson wrote:
On Fri, Sep 25, 2009 at 11:57 AM, Stefan Reinauer <stepan@coresystems.de
wrote:
But your reasons are very sound. It's quite a lot of cbfs accesses, and generally I guess walking the device tree (in coreboot it's even a memory op, and not a pci config space op) is cheaper than walking all of the rom all of the time..
It's not a show-stopper for me, but I thought I'd bring it up when I came to it.
Given that ages ago my proposal to add caching for LAR entries was rejected (and I don't think positions have changed since then), LAR/ CBFS walking will stay somewhat expensive. You could build a special-case cache of LAR entries for PCI option ROMs and hope nobody remembers the original rejections. It would definitely speed up things a lot, while saving you the trouble of changing the current option ROM init model.
I don't think we do have a problem just yet... Let's not add another layer of complexity to fight the one that *might* be there... For now the biggest waste of time is just extensive while uninformative because repetetive serial output.
Stefan
Regards, Carl-Daniel