On 07.07.2009 23:03, Myles Watson wrote:
Just for my interest, but why does someone need to power on a system while holding the reset button?
In this case it is to allow my FPGA time to initialize (or for me to reprogram it) before the Opteron tries to set up HyperTransport communication with it.
I have no idea if the reset button directly triggers a reset line or something similar on the processor, but it would be interesting to know: 1. Does the power off also happen if you hold reset after the machine has already been booted? (Do n seconds of reset always trigger a poweroff?) 2. Which part of the board reacts to the held reset line and triggers the poweroff? 3. Is reset maybe somehow coupled to PWRGOOD and holding down reset is perceived as electrical problem of the power supply?
Regards, Carl-Daniel