I am trying to understand the Opteron Address Map, and am having some problems. I'm pretty sure I understand everything but the PCI I/O section, but I have few questions about the other sections also. If there is a good document to help one setup the address map, other than the "AMD BIOS and Kernel Developer's Guide", please let me know.
I have a Quad-Opteron system, with an AMD 8131 and AMD 8111 hanging off of CPU 0, and another AMD 8131 hanging off of CPU 1. Each CPU has 4 DIMM slots for DDR memory.
1. Does the DRAM map section pertain to the DDR SDRAM, or is there an ability on the Opteron (as on some other PPC processors I have dealt with) to hang standard DRAM off of the local bus of the processor? If this is for DDR SDRAM, if I leave them all disabled, do these get configured later when the BIOS reads the SPD PROM for the DDR? Or do I have to configure a Window for each processor's maximum allowable DDR SDRAM?
2. It seems that the Memory Mapped I/O section is mainly to map the AMD 8111 and 8131s IO-APIC address ranges (which seem to be 64KB in size). Is this correct, and is there anything else that should go there (maybe PCI space)?
3. The PCI I/O section is my main problem. I haven't dealt with PCI too much in depth. I don't understand how it uses only 13 bits for the PCI I/O Base and Limit addresses? I thought that you need a 32-bit address? Please help me understand exactly what the I/O base address is! The only examples in the LinuxBIOS tree have the AMD 8111 & 8131s hanging off of one CPU, and therefor just steer all of the address range to that HT link.
Thanks you in advance!
Jeff Stevens
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