Solved with the help of @icon__ at the IRC channel.
The crucial part was to change disable_mask bit from 0x87 to 0x83 in src/mainboard/lenovo/t420/devicetree.cb: line 88.
Thank you for your support @icon__!
On April 9, 2020 3:21:42 PM UTC, AreYouLoco? areyouloco@paranoici.org wrote:
I did try this (patch format) but it still didn't work. It adds correct pci_device_id and tries to enable it in devicetree.cb:
From 3f60158b5b19400f2f705b41411cd9c88517328d Mon Sep 17 00:00:00 2001 From: AreYouLoco areyouloco@paranoici.org Date: Thu, 9 Apr 2020 17:17:18 +0200 Subject: [PATCH] Initial changes to support Ricoh Co Ltd R5C832 PCIe IEEE 1394 Controller
src/drivers/ricoh/rce822/rce822.c | 4 ++-- src/mainboard/lenovo/t420/devicetree.cb | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index fb714c2406..44c8538094 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -50,7 +50,7 @@ static struct device_operations rce822_ops = { .ops_pci = &lops_pci, };
-static const unsigned short pci_device_ids[] = { 0xe822, 0xe823, 0 }; +static const unsigned short pci_device_ids[] = { 0xe822, 0xe823, 0xe832, 0 };
static const struct pci_driver rce822 __pci_driver = { .ops = &rce822_ops, @@ -59,5 +59,5 @@ static const struct pci_driver rce822 __pci_driver = { };
struct chip_operations drivers_ricoh_rce822_ops = {
- CHIP_NAME("RICOH RCE822")
- CHIP_NAME("RICOH RCE822s")
}; diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5a96..7d256f9df7 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -86,7 +86,8 @@ chip northbridge/intel/sandybridge chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87"
device pci 00.0 on end
device pci 00.0 on end # Ricoh Co Ltd MMC/SD Host Controllerdevice pci 00.3 on end # Ricoh Co Ltd PCIe IEEE 1394 Controller end end # PCIe Port #5 (Ricoh SD & FW) device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY(not PCIe)