[coreboot] Q on flashing IFD from within coreboot (IVB boards)

[Keith Hui]

I have narrowed the IFD update logic to one UEFI module within vendor
BIOS: PcieLaneDxe, and after running Ghidra on it, I have learned
enough to start implementing it on coreboot.

All is in pursuit of this:
https://review.coreboot.org/c/coreboot/+/85413

It will also help with the recently upstream p8z77-v_le_plus, and
Sabertooth Z77.

Turns out vendor is also just reflashing the IFD after configuring
some GPIOs on the board. They don't seem concerned about SPI
controller freezing.

My code is going to look like this:

8<------
static enum cb_err reprogram_ifd(u8 new_pciepcs1)
{
    const unsigned int PCHSTRP9 = 0x124;
    u16 lvscc = RCBA16(0x38c4);
    const unsigned int lbes_map[] = { 256, 4 * KiB, 8 * KiB, 64 * KiB };
    u8 * ifdbuf;
    u8 erase_opcode = (lvscc >> 8) & 0xff;
    unsigned int erase_size = lbes_map[lvscc & 0b11];
    unsigned int i;

ifdbuf = malloc(erase_size);
    /* Read */
    memcpy(ifdbuf, (void *) 0xff800000, erase_size);
    /* Patch */
    ifdbuf[PCHSTRP9] &= 0b11111100;
    ifdbuf[PCHSTRP9] |= (pciepcs1 & 0b11);
    /* Erase */
    /* Write */
    for (i = 0; i < erase_size; i+=64) {
        if (is_write_needed (ifdbuf+i, 64) {
            /* Write all 64 bytes if anything within isn't 0xff */
        }
    }

free(ifdbuf);
    return CB_SUCCESS;
}
8<------

Q1: So far all boards in the Asus p8x7x-series family that need this
use 8MiB SPI flash, so they're mapped to 0xff800000 when run as
32-bit. What is the right address to use when coreboot is compiled as
64-bit? Would I have to do "max int - 8 MiB"?

Q2: I may have asked this before. Can I use SPI_FLASH Kconfig and the
SPI flash driver? Can I use this without a FMD file? Or am I better
off rolling my own again?

Thanks
Keith