Hi,
this patch adds main support for BCOM's Winnet100 Geode GX1 based terminal. It activates the VGA support so it would be possible to run this target as a small (and silent) X terminal. With faster SDRAM timing (not yet supported in mainline) it can run graphical resolutions up to SXGA (1280x1024) at 64k colours.
I'm not sure if all files I add to src/mainboard/bcom/winnet100 are required. Most of them are copies from other GX1 based mainboards.
Tested on my IGEL316 terminal (=BCOM Winnet100) with 64MiB SDRAM, kernel 2.6.22 and Xorg 7.1.
Juergen
Subject: Adding BCOM Winnet100
From: Juergen Beisert juergen@kreuzholzen.de
This patch adds BCOM's winnet100 to the supported mainboards. Refer http://www.linuxbios.org/index.php/BCOM_WINNET100_Build_Tutorial for hardware description.
Patch is against LinuxBIOSv2, revision of 2007-10-09
Signed-off-by: Juergen Beisert juergen@kreuzholzen.de
---
Index: src/mainboard/bcom/winnet100/Config.lb =================================================================== --- src/mainboard/bcom/winnet100/Config.lb (Revision 0) +++ src/mainboard/bcom/winnet100/Config.lb (Revision 0) @@ -0,0 +1,180 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size of +## the linuxBIOS bootloader. +## +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE object irq_tables.o end + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + device pci 12.0 on + chip superio/nsc/pc97317 + device pnp 2e.0 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # FDC + end + device pnp 2e.4 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power Management + io 0x60 = 0xe800 + end + register "com1" = "{115200}" + register "com2" = "{38400}" + end + device pci 12.1 off end # SMI + device pci 12.2 off end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA +# device pci 13.0 on end # USB + end + end + end + + chip cpu/amd/model_gx1 + end + +end Index: src/mainboard/bcom/winnet100/irq_tables.c =================================================================== --- src/mainboard/bcom/winnet100/irq_tables.c (Revision 0) +++ src/mainboard/bcom/winnet100/irq_tables.c (Revision 0) @@ -0,0 +1,116 @@ +/** + * @file + * @brief Interrupt routing description for BCOM's Winnet100 board + * It was not possible to read back the pirq-Table. In the 0xF segment was + * no string like $PIRQ... + * But the already running 2.4.21 kernel provides eth0 IRQ15 and USB IRQ 11 + * The Realtek was device 0.f.0, the usb 0.13.0 + * + * This is the physical routing on this board: + * + * 5530 USB Network + * northbridge device device + * 00.13.0 00.0f.00 + * ------------------------------------ + * INTA# INTA# n.c. + * INTB# n.c. n.c. + * INTC# n.c. INTA# + * INTD# n.c. n.c. + */ + +#include <arch/pirq_routing.h> + + +/* + * the USB controller should be connected to IRQ11 + * the network controller should be connected to IRQ15 + */ + +#define IRQ_BITMAP_LINK0 0x0800 +#define IRQ_BITMAP_LINK1 0x0400 +#define IRQ_BITMAP_LINK2 0x8000 +#define IRQ_BITMAP_LINK3 0x0200 + +/** + * Routing desciption. + * Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx + */ +const struct irq_routing_table intel_irq_routing_table = { + .signature = PIRQ_SIGNATURE, /* u32 signature */ + .version = PIRQ_VERSION, /* u16 version */ + .size = 32+16*IRQ_SLOT_COUNT, /* there can be total 2 devices on the bus */ + .rtr_bus = 0x00, /* Where the interrupt router lies (bus) */ + .rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + .exclusive_irqs = 0x8800, /* IRQs devoted exclusively to PCI usage */ + .rtr_vendor = 0x1078, /* Vendor */ + .rtr_device = 0x0100, /* Device */ + .miniport_data = 0, /* Crap (miniport) */ + .checksum = 0xBF+16, +/* + * Definition for "slot#1". There is no real slot, + * the USB device is embedded... + */ + .slots = { + [0] = { + .bus = 0x00, + .devfn = (0x13<<3)|0x0, + .irq = { + [0] = { + .link = 0x01, /* INT A */ + .bitmap = IRQ_BITMAP_LINK0 + }, + [1] = { + .link = 0x02, /* INT B */ + .bitmap = IRQ_BITMAP_LINK1 + }, + [2] = { + .link = 0x03, /* INT C */ + .bitmap = IRQ_BITMAP_LINK2 + }, + [3] = { + .link = 0x04, /* INT D */ + .bitmap = IRQ_BITMAP_LINK3 + } + }, + .slot = 0x0, + }, +/* + * Definition for "slot#3". There is no real slot, + * the network device is soldered... + */ + [1] = { + .bus = 0x00, + .devfn = (0x0f<<3)|0x0, + .irq = { + [0] = { + .link = 0x03, + .bitmap = IRQ_BITMAP_LINK2 + }, + [1] = { + .link = 0x04, + .bitmap = IRQ_BITMAP_LINK3 + }, + [2] = { + .link = 0x01, + .bitmap = IRQ_BITMAP_LINK0 + }, + [3] = { + .link = 0x02, + .bitmap = IRQ_BITMAP_LINK1 + } + }, + .slot = 0x0, + } + } +}; + +/** + * copy the IRQ routing table to memory + * @param[in] addr destination address (between 0xF0000...0x100000) + **/ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} + +/* end of file irq_tables.c */ Index: src/mainboard/bcom/winnet100/Options.lb =================================================================== --- src/mainboard/bcom/winnet100/Options.lb (Revision 0) +++ src/mainboard/bcom/winnet100/Options.lb (Revision 0) @@ -0,0 +1,170 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_VIDEO_MB +uses CONFIG_SPLASH_GRAPHIC +uses CONFIG_GX1_VIDEO +uses CONFIG_GX1_VIDEOMODE + +## +## Enable VGA with a splash screen +## but only 640x480 to run on nearly all monitors +## + +default CONFIG_GX1_VIDEO=1 +default CONFIG_GX1_VIDEOMODE=0 +default CONFIG_SPLASH_GRAPHIC=1 + +## +## We want to support up to 1024x768@16 so we need +## 2MiB video memory. Note: Higher resolutions might +## need faster SDRAM speed. +## + +default CONFIG_VIDEO_MB=2 + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=2 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc " +default HOSTCC="gcc" + +## +## The Serial Console +## + +## To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 + +## Select the serial console base port +default TTYS0_BASE=0x3f8 + +## Select the serial protocol +## This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=6 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=6 + +end Index: src/mainboard/bcom/winnet100/failover.c =================================================================== --- src/mainboard/bcom/winnet100/failover.c (Revision 0) +++ src/mainboard/bcom/winnet100/failover.c (Revision 0) @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} Index: src/mainboard/bcom/winnet100/auto.c =================================================================== --- src/mainboard/bcom/winnet100/auto.c (Revision 0) +++ src/mainboard/bcom/winnet100/auto.c (Revision 0) @@ -0,0 +1,54 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann uwe@hermann-uwe.de + * Modyfied by Juergen Beisert juergen@kreuzholzen.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/gx1/raminit.c" +#include "superio/nsc/pc97317/pc97317_early_serial.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + /* Initialize RAM. */ + sdram_init(); + + /* Check whether RAM works. */ + /* ram_check(0x00000000, 0x4000); */ +} Index: src/mainboard/bcom/winnet100/chip.h =================================================================== --- src/mainboard/bcom/winnet100/chip.h (Revision 0) +++ src/mainboard/bcom/winnet100/chip.h (Revision 0) @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_bcom_winnet100_ops; + +struct mainboard_bcom_winnet100_config { + int nothing; +}; Index: src/mainboard/bcom/winnet100/cmos.layout =================================================================== --- src/mainboard/bcom/winnet100/cmos.layout (Revision 0) +++ src/mainboard/bcom/winnet100/cmos.layout (Revision 0) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Index: src/mainboard/bcom/winnet100/mainboard.c =================================================================== --- src/mainboard/bcom/winnet100/mainboard.c (Revision 0) +++ src/mainboard/bcom/winnet100/mainboard.c (Revision 0) @@ -0,0 +1,11 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "chip.h" + +struct chip_operations mainboard_bcom_winnet100_ops = { + CHIP_NAME("BCOM winterm100 mainboard ") +}; Index: targets/bcom/winnet100/Config.lb =================================================================== --- targets/bcom/winnet100/Config.lb (Revision 0) +++ targets/bcom/winnet100/Config.lb (Revision 0) @@ -0,0 +1,24 @@ +# Config file for the BCOM WINNET100 motherboard +# (available as IGEL-316 for example) +# Refer: http://www.linuxbios.org/index.php/BCOM_WINNET100_Build_Tutorial +# +target winnet100 +mainboard bcom/winnet100 + +option ROM_SIZE=1024*256 + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION=".0Normal" + payload ../../../../../../../images/etherboot.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" + payload ../../../../../../../images/etherboot.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"