Ronald G. Minnich (rminnich@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2467
-gerrit
commit d884827fc73108ff3005cb45b33af05b1d1c30a4 Author: Ronald G. Minnich rminnich@gmail.com Date: Wed Feb 20 15:46:46 2013 -0800
google/snow: enable GPIO entries and CHROMEOS in building
These were not separable or it would have been two CLs.
Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs.
Add a chromeos.c file for snow, needed to build.
This is tested and creates gpio table entries that our hardware can use.
Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel.
Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- src/arch/armv7/boot/coreboot_table.c | 10 ++- src/arch/armv7/include/arch/coreboot_tables.h | 2 + src/mainboard/google/snow/Kconfig | 2 +- src/mainboard/google/snow/Makefile.inc | 1 + src/mainboard/google/snow/chromeos.c | 98 +++++++++++++++++++++++++++ src/vendorcode/google/chromeos/Kconfig | 1 + src/vendorcode/google/chromeos/Makefile.inc | 6 +- 7 files changed, 110 insertions(+), 10 deletions(-)
diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 2810a5e..55610ac 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <ip_checksum.h> #include <boot/tables.h> -#include <boot/coreboot_tables.h> #include <arch/coreboot_tables.h> #include <string.h> #include <version.h> @@ -35,7 +34,7 @@ #include <option_table.h> #endif #if CONFIG_CHROMEOS -#include <arch/acpi.h> +//#include <arch/acpi.h> #include <vendorcode/google/chromeos/gnvs.h> #endif
@@ -183,11 +182,10 @@ static void lb_gpios(struct lb_header *header) struct lb_gpios *gpios; gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; - gpios->size = sizeof(*gpios); - gpios->count = 0; fill_lb_gpios(gpios); }
+#if 0 static void lb_vdat(struct lb_header *header) { struct lb_vdat* vdat; @@ -209,6 +207,7 @@ static void lb_vbnv(struct lb_header *header) vbnv->vbnv_size = CONFIG_VBNV_SIZE; } #endif +#endif
static void add_cbmem_pointers(struct lb_header *header) { @@ -656,12 +655,11 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - -#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head);
+#if 0 /* pass along the VDAT buffer adress */ lb_vdat(head);
diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index ab20866..4c2a013 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -12,6 +12,8 @@ unsigned long write_coreboot_table( void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size);
+void fill_lb_gpios(struct lb_gpios *gpios); + /* Routines to extract part so the coreboot table or information * from the coreboot table. */ diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index bee987d..6face94 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT -# select CHROMEOS + select CHROMEOS
config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index b56a1a4..668e3b7 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += romstage.c
# ramstage-y += ec.c ramstage-y += ramstage.c +ramstage-y += chromeos.c
# romstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c new file mode 100644 index 0000000..5f8e631 --- /dev/null +++ b/src/mainboard/google/snow/chromeos.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> + +#include <device/device.h> + +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 +#define WP_GPIO 6 +#define DEVMODE_GPIO 54 +#define FORCE_RECOVERY_MODE 0 +#define FORCE_DEVELOPER_MODE 0 + +#include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> + +#define GPIO_COUNT 4 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + /* Write Protect: virtual GPIO active Low */ + gpios->gpios[0].port = -1; + gpios->gpios[0].polarity = ACTIVE_LOW; + gpios->gpios[0].value = 1; + strncpy((char *)gpios->gpios[0].name,"write protect", + GPIO_MAX_NAME_LENGTH); + + /* Recovery: virtual GPIO active high */ + gpios->gpios[1].port = -1; + gpios->gpios[1].polarity = ACTIVE_HIGH; + gpios->gpios[1].value = 0; + strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + + /* Developer: virtual GPIO active high */ + gpios->gpios[2].port = -1; + gpios->gpios[2].polarity = ACTIVE_HIGH; + gpios->gpios[2].value = 1; + strncpy((char *)gpios->gpios[2].name,"developer", + GPIO_MAX_NAME_LENGTH); + + /* Was VGA Option ROM loaded? */ + gpios->gpios[3].port = -1; /* Indicate that this is a pseudo GPIO */ + gpios->gpios[3].polarity = ACTIVE_HIGH; + gpios->gpios[3].value = 0; + strncpy((char *)gpios->gpios[3].name,"oprom", GPIO_MAX_NAME_LENGTH); + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", GPIO_COUNT, gpios->size); + +} + +int get_developer_mode_switch(void) +{ + int dev_mode = 0; + + printk(BIOS_DEBUG,"FORCING DEVELOPER MODE.\n"); + + dev_mode = 1; + printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO, + dev_mode); + + return dev_mode; +} + +int get_recovery_mode_switch(void) +{ + int ec_rec_mode = 0; + + return ec_rec_mode; +} + +int get_recovery_mode_from_vbnv(void) +{ + return 1; +} diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 6242147..31094de 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -61,6 +61,7 @@ config FLASHMAP_OFFSET hex "Flash Map Offset" default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE + default 0 help Offset of flash map in firmware image
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 967db96..8ae14fd 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -19,9 +19,9 @@
romstage-y += chromeos.c ramstage-y += chromeos.c -romstage-y += vbnv.c -ramstage-y += vbnv.c -romstage-y += vboot.c +romstage-$(CONFIG_ARCH_X86) += vbnv.c +ramstage-$(CONFIG_ARCH_X86) += vbnv.c +romstage-$(CONFIG_ARCH_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c