[coreboot] [commit] r5492 - in trunk/src: mainboard/asus/a8v-e_se mainboard/gigabyte/m57sli northbridge/amd/amdk8 northbridge/via/cn400 northbridge/via/cx700 northbridge/via/vx800 southbridge/amd/rs780 southb...

[repository service]

Author: stepan
Date: Sun Apr 25 15:54:30 2010
New Revision: 5492
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5492

Log:
zero warnings days

Signed-off-by: Stefan Reinauer 
Acked-by: Stefan Reinauer

Modified:
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/fanctl.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/northbridge/amd/amdk8/exit_from_self.c
   trunk/src/northbridge/amd/amdk8/raminit.h
   trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
   trunk/src/northbridge/via/cn400/vga.c
   trunk/src/northbridge/via/cx700/cx700_vga.c
   trunk/src/northbridge/via/cx700/northbridge.h
   trunk/src/northbridge/via/vx800/northbridge.h
   trunk/src/southbridge/amd/rs780/rs780_gfx.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
   trunk/src/superio/ite/it8716f/it8716f.h
   trunk/src/superio/ite/it8716f/it8716f_early_init.c
   trunk/src/superio/ite/it8716f/it8716f_early_serial.c
   trunk/src/superio/ite/it8716f/superio.c

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -80,7 +80,8 @@
 {
 }

-static void soft_reset(void)
+#include <reset.h>
+void soft_reset(void)
 {
    uint8_t tmp;

@@ -98,6 +99,9 @@
    }
 }

+// defines S3_NVRAM_EARLY:
+#include "southbridge/via/k8t890/k8t890_early_car.c"
+
 #define K8_4RANK_DIMM_SUPPORT 1

#include "northbridge/amd/amdk8/amdk8.h"
@@ -107,7 +111,6 @@
 #include "lib/generic_sdram.c"

#include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/via/k8t890/k8t890_early_car.c"

#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"

Modified: trunk/src/mainboard/gigabyte/m57sli/fanctl.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/fanctl.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/mainboard/gigabyte/m57sli/fanctl.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -1,5 +1,6 @@
 #include <arch/io.h>
 #include <stdlib.h>
+#include <superio/ite/it8716f/it8716f.h>

static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)
 {

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -98,16 +98,6 @@
    return smbus_read_byte(device, address);
 }

-#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/raminit_f.c"
-#include "lib/generic_sdram.c"
-
-#include "resourcemap.c" 
-
-#include "cpu/amd/dualcore/dualcore.c"
-
 #define MCP55_NUM 1
 #define MCP55_USE_NIC 1
 #define MCP55_USE_AZA 1
@@ -125,6 +115,18 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"

+
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "lib/generic_sdram.c"
+
+#include "resourcemap.c" 
+
+#include "cpu/amd/dualcore/dualcore.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"

#include "cpu/amd/model_fxx/init_cpus.c"

Modified: trunk/src/northbridge/amd/amdk8/exit_from_self.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/exit_from_self.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/northbridge/amd/amdk8/exit_from_self.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#include "raminit.h"
+
 void exit_from_self(int controllers, const struct mem_controller *ctrl,
    	    struct sys_info *sysinfo)
 {

Modified: trunk/src/northbridge/amd/amdk8/raminit.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit.h	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/northbridge/amd/amdk8/raminit.h	Sun Apr 25 15:54:30 2010	(r5492)
@@ -11,6 +11,9 @@
    uint16_t channel1[DIMM_SOCKETS];
 };

+struct sys_info;
+void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo);
+
 #if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1
 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
 #else

Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -1829,12 +1829,12 @@
 //int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 //int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #else
-static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+static inline int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
    return nvram_pos;
 }

-static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
    die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");

Modified: trunk/src/northbridge/via/cn400/vga.c
==============================================================================
--- trunk/src/northbridge/via/cn400/vga.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/northbridge/via/cn400/vga.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -80,12 +80,12 @@
 static void vga_init(device_t dev)
 {
    u8 reg8;
-	u32 temp;

mainboard_interrupt_handlers(0x15, &via_cn400_int15_handler);

#undef OLD_BOCHS_METHOD
 #ifdef OLD_BOCHS_METHOD
+	u32 temp;
    // XXX We might need more bios hooks in the f segment, but
    // this way of copying the BOCHS BIOS does not work anymore.
    // As soon as someone verifies that CN400 can init VGA, the

Modified: trunk/src/northbridge/via/cx700/cx700_vga.c
==============================================================================
--- trunk/src/northbridge/via/cx700/cx700_vga.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/northbridge/via/cx700/cx700_vga.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -81,7 +81,8 @@
    return res;
 }

-void write_protect_vgabios(void)
+#ifdef UNUSED_CODE
+static void write_protect_vgabios(void)
 {
    device_t dev;

@@ -95,6 +96,7 @@
    if (dev)
    	pci_write_config8(dev, 0x61, 0xff);
 }
+#endif

static void vga_init(device_t dev)
 {

Modified: trunk/src/northbridge/via/cx700/northbridge.h
==============================================================================
--- trunk/src/northbridge/via/cx700/northbridge.h	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/northbridge/via/cx700/northbridge.h	Sun Apr 25 15:54:30 2010	(r5492)
@@ -21,5 +21,6 @@
 #define NORTHBRIDGE_VIA_CX700_H

extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max);
+extern void (*vga_enable_console)(void) __attribute__((regparm(0)));

#endif				/* NORTHBRIDGE_VIA_CX700_H */

Modified: trunk/src/northbridge/via/vx800/northbridge.h
==============================================================================
--- trunk/src/northbridge/via/vx800/northbridge.h	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/northbridge/via/vx800/northbridge.h	Sun Apr 25 15:54:30 2010	(r5492)
@@ -21,5 +21,6 @@
 #define NORTHBRIDGE_VIA_VX800_H

extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max);
+extern void (*vga_enable_console)(void) __attribute__((regparm(0)));

#endif				/* NORTHBRIDGE_VIA_VX800_H */

Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_gfx.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/southbridge/amd/rs780/rs780_gfx.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -122,6 +122,7 @@
 #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
 #define MMIO_ATTRIB_SKIP_ZERO 1<<2

+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
 static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 {
    int i;
@@ -180,7 +181,6 @@
    return n;
 }

-#ifdef DONT_TRUST_RESOURCE_ALLOCATION
 static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 {
    CIM_STATUS Status = CIM_UNSUPPORTED;

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -19,6 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#include <reset.h>
+
 static unsigned get_sbdn(unsigned bus)
 {
    device_t dev;
@@ -33,7 +35,15 @@

}

-static void hard_reset(void)
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x02, 0x0cf9);
+	outb(0x06, 0x0cf9);
+}
+
+void hard_reset(void)
 {
    set_bios_reset();

@@ -41,20 +51,10 @@
    outb(0x0a, 0x0cf9);
    outb(0x0e, 0x0cf9);
 }
+
 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
-/* default value for mcp55 is good */
+	/* default value for mcp55 is good */
    /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
-
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-#if 1
-	/* link reset */
-	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
 }

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -21,6 +21,7 @@

static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val);

+#ifdef UNUSED_CODE
 static int set_ht_link_mcp55(uint8_t ht_c_num)
 {
    unsigned vendorid = 0x10de;
@@ -51,6 +52,7 @@
    outl(val, control);

}
+#endif

/* SIZE 0x100 */
 #define ANACTRL_IO_BASE	0x2800
@@ -131,14 +133,6 @@

}
-static void delayx(uint8_t value) {
-#if 1
-	int i;
-	for(i=0;i<0x8000;i++) {
-		outb(value, 0x80);
-	}
-#endif
-}

static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
 {
@@ -169,15 +163,15 @@
    tgio_ctrl |= (pci_e_x<<4)|(1<<8);
    outl(tgio_ctrl, anactrl_io_base + 0xcc);

-//	wait 100us
-	delayx(1);
+	// wait 100us
+	udelay(100);

dword = pci_read_config32(dev, 0xe4);
    dword &= ~(0x3f0); // enable
    pci_write_config32(dev, 0xe4, dword);

-//	need to wait 100ms
-	delayx(1000);
+	// need to wait 100ms
+	mdelay(100);
 }

static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -31,13 +31,13 @@
 {
    device_t dev;
    dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
-#if 0
+
    if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\n");
+		printk(BIOS_WARNING, "SMBUS controller not found\n");
+	} else {
+		printk(BIOS_DEBUG, "SMBus controller enabled\n");
    }

-	print_debug("SMBus controller enabled\n");
-#endif
    /* set smbus iobase */
    pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
    pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1);
@@ -48,36 +48,42 @@
    outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
 }

-static int smbus_recv_byte(unsigned device)
+static inline int smbus_recv_byte(unsigned device)
 {
    return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
 }
-static int smbus_send_byte(unsigned device, unsigned char val)
+
+static inline int smbus_send_byte(unsigned device, unsigned char val)
 {
    return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
 }
-static int smbus_read_byte(unsigned device, unsigned address)
+
+static inline int smbus_read_byte(unsigned device, unsigned address)
 {
    return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
 }
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+
+static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
 {
    return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
 }

-static int smbusx_recv_byte(unsigned smb_index, unsigned device)
+static inline int smbusx_recv_byte(unsigned smb_index, unsigned device)
 {
    return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device);
 }
-static int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val)
+
+static inline int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val)
 {
    return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val);
 }
-static int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address)
+
+static inline int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address)
 {
    return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address);
 }
-static int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val)
+
+static inline int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val)
 {
    return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val);
 }

Modified: trunk/src/superio/ite/it8716f/it8716f.h
==============================================================================
--- trunk/src/superio/ite/it8716f/it8716f.h	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/superio/ite/it8716f/it8716f.h	Sun Apr 25 15:54:30 2010	(r5492)
@@ -21,6 +21,9 @@
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
 /* Status: Untested on real hardware, but it compiles. */

+#ifndef SUPERIO_ITE_IT8716F_IT8716F_H
+#define SUPERIO_ITE_IT8716F_IT8716F_H
+
 #define IT8716F_FDC  0x00 /* Floppy */
 #define IT8716F_SP1  0x01 /* Com1 */
 #define IT8716F_SP2  0x02 /* Com2 */
@@ -32,3 +35,16 @@
 #define IT8716F_MIDI 0x08 /* MIDI port */
 #define IT8716F_GAME 0x09 /* GAME port */
 #define IT8716F_IR   0x0a /* Consumer IR */
+
+#if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
+/* provided by mainboard, called by it8716f superio.c */
+void init_ec(uint16_t base);
+#endif
+
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+void it8716f_disable_dev(device_t dev);
+void it8716f_enable_dev(device_t dev, unsigned iobase);
+void it8716f_enable_serial(device_t dev, unsigned iobase);
+#endif
+
+#endif

Modified: trunk/src/superio/ite/it8716f/it8716f_early_init.c
==============================================================================
--- trunk/src/superio/ite/it8716f/it8716f_early_init.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/superio/ite/it8716f/it8716f_early_init.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -22,13 +22,13 @@
 #include <arch/romcc_io.h>
 #include "it8716f.h"

-static void it8716f_disable_dev(device_t dev)
+void it8716f_disable_dev(device_t dev)
 {
    pnp_set_logical_device(dev);
    pnp_set_enable(dev, 0);
 }

-static void it8716f_enable_dev(device_t dev, unsigned iobase)
+void it8716f_enable_dev(device_t dev, unsigned iobase)
 {
    pnp_set_logical_device(dev);
    pnp_set_enable(dev, 0);

Modified: trunk/src/superio/ite/it8716f/it8716f_early_serial.c
==============================================================================
--- trunk/src/superio/ite/it8716f/it8716f_early_serial.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/superio/ite/it8716f/it8716f_early_serial.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -59,7 +59,7 @@
    pnp_write_config(dev, 0x02, 0x02);
 }

-static void it8716f_enable_serial(device_t dev, unsigned iobase)
+void it8716f_enable_serial(device_t dev, unsigned iobase)
 {
    pnp_enter_ext_func_mode(dev);
    pnp_set_logical_device(dev);

Modified: trunk/src/superio/ite/it8716f/superio.c
==============================================================================
--- trunk/src/superio/ite/it8716f/superio.c	Sun Apr 25 13:57:21 2010	(r5491)
+++ trunk/src/superio/ite/it8716f/superio.c	Sun Apr 25 15:54:30 2010	(r5492)
@@ -51,9 +51,7 @@
    pnp_write_config(dev, 0x02, 0x02);
 }

-#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
-extern void init_ec(uint16_t base);
-#else
+#if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
 static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value)
 {
    outb(reg, port_base);