[moving to coreboot@]
On 15.05.2009 00:58, Ward Vandewege wrote:
On Thu, May 14, 2009 at 11:13:45PM +0200, Carl-Daniel Hailfinger wrote:
Can you please run flashrom -V and mail the output to us? This will help us to add support for your chip.
On 14.05.2009 23:00, wangji wrote:
./flashrom -r YellowPc.rom flashrom v0.9.0-r510 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Calibrating delay loop... OK. Found chip "EON unknown EON SPI chip" (0 KB) at physical address 0x0.
Great. First time that the unknown chip logic triggered and it was immediately useful.
=== This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE Please email a report to flashrom@coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! ===
-> would it make sense to suggest to the user to write to us with flashrom -V output, since we want that output to debug almost all problems?
Indeed. We should also tell the user not to reboot and mail us or join IRC if any modifying operation fails.
My medium-term plan is to have flashrom read the flash before any erase or write (with opt-out possibility) and if erase fails halfway through, try to restore.
Regards, Carl-Daniel