Re: [coreboot] [PATCH] Clean up DBM690T and Pistachio

[Zheng Bao]

We used pci_cf8_conf1.{read,write}{8,16,32} because the pci_read_config32 doesnt
work in mainboard stage according to our test result. I dont know the current status.
We havent merge the code from comunity in weeks. And I havent test the patch. But 
I think, I just think it will not work.

Zheng> Date: Fri, 13 Feb 2009 11:54:57 +0100> From: [e-mail]> To: [e-mail]> Subject: [coreboot] [PATCH] Clean up DBM690T and Pistachio> > Clean up DBM690T and Pistachio targets:> - Use MAINBOARD_VENDOR and MAINBOARD_PART_NUMBER wherever possible> instead of filling out the strings by hand.> - Avoid using the mainboard name in function names unless explicitly> required by the build system.> - Use pci_{read,write}_config{8,16,32} instead of> pci_cf8_conf1.{read,write}{8,16,32} in mainboard.c.> - Remove unused variables.> - Improve accuracy of some thermal comments.> - Improve formatting and formatting consistency.> > With this patch, porting to a new AMD 690/SB600 board becomes even> easier because there is less stuff to replace. A nice side effect is> that the mainboard directories of DBM690T and Pistachio are now almost> identical.> > No functional changes. Compile tested. (You have to revert r3942 to get> any 690/SB600 target to compile. Simply run "svn diff -c 3942|patch -p0> -R" in the main source directory.)> > Signed-off-by: Carl-Daniel Hailfinger > > Index: corebootv2/src/mainboard/amd/pistachio/resourcemap.c> ===================================================================> --- corebootv2/src/mainboard/amd/pistachio/resourcemap.c (revision 3943)> +++ corebootv2/src/mainboard/amd/pistachio/resourcemap.c (working copy)> @@ -17,7 +17,7 @@> * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA> */> > -static void setup_pistachio_resource_map(void)> +static void setup_mb_resource_map(void)> {> static const unsigned int register_values[] = {> /* Careful set limit registers before base registers which contain the enables */> Index: corebootv2/src/mainboard/amd/pistachio/chip.h> ===================================================================> --- corebootv2/src/mainboard/amd/pistachio/chip.h (revision 3943)> +++ corebootv2/src/mainboard/amd/pistachio/chip.h (working copy)> @@ -21,6 +21,6 @@> > struct mainboard_amd_pistachio_config> {> - unsigned long uma_size; /* How many UMA should be used in memory for TOP. */> + u32 uma_size; /* How many UMA should be used in memory for TOP. */> };> > Index: corebootv2/src/mainboard/amd/pistachio/mainboard.c> ===================================================================> --- corebootv2/src/mainboard/amd/pistachio/mainboard.c (revision 3943)> +++ corebootv2/src/mainboard/amd/pistachio/mainboard.c (working copy)> @@ -83,7 +83,6 @@> u16 word;> u32 dword;> device_t sm_dev;> - struct bus pbus;> > /* set adt7475 */> ADT7475_write_byte(0x40, 0x04);> @@ -116,11 +115,11 @@> /* remote 2 therm temp limit (95C) */> ADT7475_write_byte(0x6c, 0x9f);> > - /* PWM 1 minimum duty cycle (37%) */> + /* PWM 1 minimum duty cycle (37.6%) */> ADT7475_write_byte(0x64, 0x60);> /* PWM 1 Maximum duty cycle (100%) */> ADT7475_write_byte(0x38, 0xff);> - /* PWM 3 minimum duty cycle (37%) */> + /* PWM 3 minimum duty cycle (37.6%) */> ADT7475_write_byte(0x66, 0x60);> /* PWM 3 Maximum Duty Cycle (100%) */> ADT7475_write_byte(0x3a, 0xff);> @@ -167,28 +166,19 @@> > /* GPM5 as GPIO not USB OC */> sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));> - dword => - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x64);> + dword = pci_read_config32(sm_dev, 0x64);> dword |= 1 << 19;> - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x64, dword);> + pci_write_config32(sm_dev, 0x64, dword);> > /* Enable Client Management Index/Data registers */> - dword => - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x78);> + dword = pci_read_config32(sm_dev, 0x78);> dword |= 1 << 11; /* Cms_enable */> - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x78, dword);> + pci_write_config32(sm_dev, 0x78, dword);> > /* MiscfuncEnable */> - byte => - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x41);> + byte = pci_read_config8(sm_dev, 0x41);> byte |= (1 << 5);> - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x41, byte);> + pci_write_config8(sm_dev, 0x41, byte);> > /* set GPM5 as input */> /* set index register 0C50h to 13h (miscellaneous control) */> @@ -228,12 +218,9 @@> pm2_iowrite(0x42, byte);> > /* set GPIO 64 to input */> - word => - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x56);> + word = pci_read_config16(sm_dev, 0x56);> word |= 1 << 7;> - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x56, word);> + pci_write_config16(sm_dev, 0x56, word);> > /* set GPIO 64 internal pull-up */> byte = pm2_ioread(0xf0);> @@ -269,12 +256,12 @@> * enable the dedicated function in pistachio board.> * This function called early than rs690_enable.> *************************************************/> -void pistachio_enable(device_t dev)> +void mb_enable(device_t dev)> {> struct mainboard_amd_pistachio_config *mainboard => (struct mainboard_amd_pistachio_config *)dev->chip_info;> > - printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev);> + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=0x%x\n", dev);> > #if (CONFIG_GFXUMA == 1)> msr_t msr, msr2;> @@ -339,6 +326,6 @@> * CONFIG_CHIP_NAME defined in Option.lb.> */> struct chip_operations mainboard_amd_pistachio_ops = {> - CHIP_NAME("AMD Pistachio Mainboard")> - .enable_dev = pistachio_enable,> + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")> + .enable_dev = mb_enable,> };> Index: corebootv2/src/mainboard/amd/pistachio/cache_as_ram_auto.c> ===================================================================> --- corebootv2/src/mainboard/amd/pistachio/cache_as_ram_auto.c (revision 3943)> +++ corebootv2/src/mainboard/amd/pistachio/cache_as_ram_auto.c (working copy)> @@ -156,9 +156,8 @@> u32 bsp_apicid = 0;> msr_t msr;> struct cpuid_result cpuid1;> - struct sys_info *sysinfo => - (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -> - DCACHE_RAM_GLOBAL_VAR_SIZE);> + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +> + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);> > if (bist == 0) {> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);> @@ -178,7 +177,7 @@> report_bist_failure(bist);> printk_debug("bsp_apicid=0x%x\n", bsp_apicid);> > - setup_pistachio_resource_map();> + setup_mb_resource_map();> > setup_coherent_ht_domain();> > Index: corebootv2/src/mainboard/amd/dbm690t/irq_tables.c> ===================================================================> --- corebootv2/src/mainboard/amd/dbm690t/irq_tables.c (revision 3943)> +++ corebootv2/src/mainboard/amd/dbm690t/irq_tables.c (working copy)> @@ -54,7 +54,7 @@> extern u8 bus_isa;> extern u8 bus_rs690[8];> extern u8 bus_sb600[2];> -extern unsigned long sbdn_sb600;> +extern u32 sbdn_sb600;> > unsigned long write_pirq_routing_table(unsigned long addr)> {> Index: corebootv2/src/mainboard/amd/dbm690t/resourcemap.c> ===================================================================> --- corebootv2/src/mainboard/amd/dbm690t/resourcemap.c (revision 3943)> +++ corebootv2/src/mainboard/amd/dbm690t/resourcemap.c (working copy)> @@ -17,7 +17,7 @@> * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA> */> > -static void setup_dbm690t_resource_map(void)> +static void setup_mb_resource_map(void)> {> static const unsigned int register_values[] = {> /* Careful set limit registers before base registers which contain the enables */> Index: corebootv2/src/mainboard/amd/dbm690t/mainboard.c> ===================================================================> --- corebootv2/src/mainboard/amd/dbm690t/mainboard.c (revision 3943)> +++ corebootv2/src/mainboard/amd/dbm690t/mainboard.c (working copy)> @@ -99,30 +99,21 @@> u8 byte;> /*u32 sm_dev, ide_dev; */> device_t sm_dev, ide_dev;> - struct bus pbus;> > sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));> > - byte => - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0xA9);> + byte = pci_read_config8(sm_dev, 0xA9);> byte |= (1 << 5); /* Set Gpio9 as input */> - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0xA9, byte);> + pci_write_config8(sm_dev, 0xA9, byte);> > ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));> - byte => - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,> - ide_dev->path.u.pci.devfn, 0x56);> + byte = pci_read_config8(ide_dev, 0x56);> byte &= ~(7 << 0);> - if ((1 << 5) & pci_cf8_conf1.> - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn,> - 0xAA))> + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))> byte |= 2 << 0; /* mode 2 */> else> byte |= 5 << 0; /* mode 5 */> - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,> - ide_dev->path.u.pci.devfn, 0x56, byte);> + pci_write_config8(ide_dev, 0x56, byte);> }> > /*> @@ -133,7 +124,6 @@> u8 byte;> u16 word;> device_t sm_dev;> - struct bus pbus;> > /* set ADT 7461 */> ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */> @@ -156,12 +146,9 @@> > /* set GPIO 64 to input */> sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));> - word => - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x56);> + word = pci_read_config16(sm_dev, 0x56);> word |= 1 << 7;> - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,> - sm_dev->path.u.pci.devfn, 0x56, word);> + pci_write_config16(sm_dev, 0x56, word);> > /* set GPIO 64 internal pull-up */> byte = pm2_ioread(0xf0);> @@ -197,12 +184,12 @@> * enable the dedicated function in dbm690t board.> * This function called early than rs690_enable.> *************************************************/> -void dbm690t_enable(device_t dev)> +void mb_enable(device_t dev)> {> struct mainboard_amd_dbm690t_config *mainboard => (struct mainboard_amd_dbm690t_config *)dev->chip_info;> > - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev);> + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=0x%x\n", dev);> > #if (CONFIG_GFXUMA == 1)> msr_t msr, msr2;> @@ -267,6 +254,6 @@> * CONFIG_CHIP_NAME defined in Option.lb.> */> struct chip_operations mainboard_amd_dbm690t_ops = {> - CHIP_NAME("AMD DBM690T Mainboard")> - .enable_dev = dbm690t_enable,> + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")> + .enable_dev = mb_enable,> };> Index: corebootv2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c> ===================================================================> --- corebootv2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (revision 3943)> +++ corebootv2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (working copy)> @@ -137,7 +137,7 @@> normal_image:> post_code(0x23);> __asm__ volatile ("jmp __normal_image": /* outputs */> - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);> + :"a" (bist), "b"(cpu_init_detectedx)); /* inputs */> > fallback_image:> post_code(0x25);> @@ -162,9 +162,9 @@> u32 bsp_apicid = 0;> msr_t msr;> struct cpuid_result cpuid1;> - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);> + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +> + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);> > -> if (bist == 0) {> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);> }> @@ -181,7 +181,7 @@> report_bist_failure(bist);> printk_debug("bsp_apicid=0x%x\n", bsp_apicid);> > - setup_dbm690t_resource_map();> + setup_mb_resource_map();> > setup_coherent_ht_domain();> > > > -- > http://www.hailfinger.org/%3E 
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