On Fri, Apr 09, 2010 at 09:41:59PM +0200, Stefan Reinauer wrote:
See patch
This runs on my epia-cn. However, it's a bit slower than the romcc code.
Old code timing (r5005 with caching hacks):
00.000: <00> 00.006: <00> 00.343: 00.343: 00.343: coreboot-2.3" Fri Jan 8 20:36:20 EST 2010 starting... 00.344: *pre enable_smbus() 00.402: *post enable_smbus() 00.406: *pre ddr_ram_setup() 00.422: *post ddr_ram_setup() 00.424: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @ 0x4000 00.450: coreboot-2.3 Fri Apr 2 11:56:00 EDT 2010 booting...
New code timing (r5408):
00.000: <00> 00.446: 0 00.448: 00.448: coreboot-4.0-r5408M Sun Apr 11 22:51:47 EDT 2010 starting... 00.448: *pre enable_smbus() 00.448: *post enable_smbus() 00.452: *pre ddr_ram_setup() 00.464: *post ddr_ram_setup() 00.465: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @ 0x4000 01.421: coreboot-4.0-r5408M Sun Apr 11 22:51:47 EDT 2010 booting...
The old code was also using tiny boot block, but I had hacked it a bit to enable caching early. (With CAR, I can't do the caching tricks I had earlier.)
The delay after "Stage:.." is almost certainly the setting of the stack to 0x4000000 in src/cpu/via/car/cache_as_ram.inc without caching that ram. (The same problem was in the old code, but I hacked a larger earlier cache.) I'll try the same on the new code.
The extra time to get to the "coreboot-..." banner is a bit puzzling though. The timings are reproducible, so it's not a fluke. I'll have to investigate further.
Great stuff though. Thanks. -Kevin