Nils,
You can get the errata information from the AMD embedded dev site if you want to sign up. http://wwwd.amd.com/dev.
I don't think that the GX2 has that bug and the register bit definitions are completely different. I would leave it out.
Marc
On Sun, Jun 20, 2010 at 3:42 PM, Nils njacobs8@hetnet.nl wrote:
Hi all, I ported the Geode LX Cache As Ram code to GX2. It works nice and it reduces the boot time with ~35 seconds. Though there is a piece of code i would like some more information on. It is in /src/northbridge/amd/lx/raminit.c :
/* SWAPSiF for PBZ 4112 (Errata 34) */ /* check for failed DLL settings now that we have done a memory write. */ msrnum = GLCP_DELAY_CONTROLS; msr = rdmsr(msrnum); if ((msr.lo & 0x7FF) == 0x104) {
/* If you had it you would need to clear out the fail boot count flag */ /* (depending on where it counts from etc). */
/* The reset we are about to perform clears the PM_SSC register in the */ /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */ /* it would do a normal boot */
/* Reset the system */ msrnum = MDD_SOFT_RESET; msr = rdmsr(msrnum); msr.lo |= 1; wrmsr(msrnum, msr);
I omitted this routine in my patch because i could not find a description about PBZ 4112 (Errata 34) and according to the LX databook the tested bit 8 is "Reserved".
My questions are:
- Where could i find information on "Errata 34" ?
2.Would a similar test be needed/desired for GX2 ?
Thanks,Nils.
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