Author: hailfinger Date: 2008-11-13 02:53:55 +0100 (Thu, 13 Nov 2008) New Revision: 1013
Modified: coreboot-v3/arch/x86/intel/core2/stage0.S Log: Kill v2 leftovers.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-13 01:28:32 UTC (rev 1012) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-13 01:53:55 UTC (rev 1013) @@ -64,7 +64,6 @@ movw %ax, %gs
cache_as_ram: -#if USE_FALLBACK_IMAGE == 1
port80_post(0x20)
@@ -129,7 +128,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif
/* Enable Cache As RAM mode by disabling cache */ movl %cr0, %eax