On 04/11/2010 07:11 AM, Stefan Reinauer wrote:
On 4/11/10 7:50 AM, repository service wrote:
Author: linux_junkie Date: Sun Apr 11 07:50:08 2010 New Revision: 5402 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5402
Log: Trivial changes to i82830 raminit.c for USE_PRINTK_IN_CAR. Signed-off-by: Joseph Smithjoe@settoplinux.org Acked-by: Joseph Smithjoe@settoplinux.org
Modified: trunk/src/northbridge/intel/i82830/raminit.c
Modified: trunk/src/northbridge/intel/i82830/raminit.c
--- trunk/src/northbridge/intel/i82830/raminit.c Sat Apr 10 00:25:27 2010 (r5401) +++ trunk/src/northbridge/intel/i82830/raminit.c Sun Apr 11 07:50:08 2010 (r5402) @@ -30,16 +30,10 @@
static void ram_read32(u8 dimm_start, u32 offset) { if (offset == 0x55aa55aa) {
...
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024));
There is a good chance that this read does not happen unless debugging is enabled. Is that on purpose? It would be clearer to pull this out of the PRINTK like this:
#if CONFIG_RAM_DEBUG u32 value = read32(dimm_start * 32 * 1024 * 1024); PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32
- 1024 * 1024), value);
#endif
Yes that is on purpose. I guess I could use a preprocessing directive, but I thought that was the point of the macro.
/* MRS command */ /* TODO: Set offset 0x1d0 according to DRT values */
PRINT_DEBUG(" MRS ");
PRINTK_DEBUG(" MRS\n");
You could make these PRINTK(BIOS_DEBUG, ...) instead of PRINTK_DEBUG(...) to be able to easily use different log levels with one macro.
True. If it would make the code more cleaner I could do that. Here is what it looks like with CONFIG_RAM_DEBUG enabled:
coreboot-4.0-r5401M Sun Apr 11 01:30:35 EDT 2010 starting... SMBus controller enabled Setting initial sdram registers.... Found DIMM in slot 0 DIMM is 256MB on side 1 DIMM is 256MB on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 1 DIMM is 64MB on side 1 DIMM is 0MB on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 0 DRA 0x70 has been set to 0x22 Found DIMM in slot 1 DRA 0x71 has been set to 0xf1 Initial sdram registers have been set. Initializing SDRAM Row 0 NOP Sending RAM command 0x00000010 to 0x00000000 Pre-charging all banks Sending RAM command 0x00000020 to 0x00000000 8 CBR refreshes Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 MRS Sending RAM command 0x00000030 to 0x000001d0 Normal operation mode Sending RAM command 0x00000070 to 0x00000000 Performing dummy read/write Reading RAM at 0x00000000 => 0xbd7f75ff Writing RAM at 0x00000000 <= 0x55aa55aa Reading RAM at 0x00000000 => 0x55aa55aa Initializing SDRAM Row 1 NOP Sending RAM command 0x00000010 to 0x10000000 Pre-charging all banks Sending RAM command 0x00000020 to 0x10000000 8 CBR refreshes Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x10000000 Sending RAM command 0x00000060 to 0x10000000 MRS Sending RAM command 0x00000030 to 0x100001d0 Normal operation mode Sending RAM command 0x00000070 to 0x10000000 Performing dummy read/write Reading RAM at 0x10000000 => 0x57afffff Writing RAM at 0x10000000 <= 0x55aa55aa Reading RAM at 0x10000000 => 0x55aa55aa Initializing SDRAM Row 2 NOP Sending RAM command 0x00000010 to 0x20000000 Pre-charging all banks Sending RAM command 0x00000020 to 0x20000000 8 CBR refreshes Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x20000000 Sending RAM command 0x00000060 to 0x20000000 MRS Sending RAM command 0x00000030 to 0x200001d0 Normal operation mode Sending RAM command 0x00000070 to 0x20000000 Performing dummy read/write Reading RAM at 0x20000000 => 0xf5ba55aa Writing RAM at 0x20000000 <= 0x55aa55aa Reading RAM at 0x20000000 => 0x55aa55aa Enabling Refresh Setting initialization complete Setting initial nothbridge registers.... Initial northbridge registers have been set. Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 41 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00 70: 22 f1 ff ff 00 00 00 00 10 00 00 00 70 01 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 09 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 cf 2f cf 22 cd 1e cc
And here is what it looks like when not enabled:
coreboot-4.0-r5401M Sun Apr 11 01:39:18 EDT 2010 starting... SMBus controller enabled Found DIMM in slot 0 DIMM is 256MB on side 1 DIMM is 256MB on side 2 Found DIMM in slot 1 DIMM is 64MB on side 1 DIMM is 0MB on side 2 Initializing SDRAM Row 0 Initializing SDRAM Row 1 Initializing SDRAM Row 2
Simple and clean :-)