On Friday 27 January 2012 12:08:01 Prakash Punnoor wrote:
On Tuesday 24 January 2012 22:26:31 Scott Duplichan wrote:
Prakash Punnoor wrote: ] At least the following "die(...)" statement (romstage.c ]cache_as_ram_main) suggests that program flow should NOT get there. So, if ]coreboots runs again from start, why doesn't it enable port 80 again like ]it did initially?
I am not sure. But the important function is sb7xx_51xx_pci_port80(), called from line 90 of romstage.c. It looks like that function does everything needed to enable PCI port 80. You could try calling the function unconditionally and see what happens.
Unfortunately that didn't help. So maybe coreboot isn't reaching cache_as_ram_main after soft_reset anymore. I commented out the call to soft_reset (and die) and now coreboot runs till the device init as on "warm start". Any other ideas how to make soft_reset work?
Yay, I think I solved this problem. Some amd functions are depending on the cpu type, which are read out at a different place:
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 0c01cf1..0d7e91e 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -197,6 +197,7 @@ u32 mctGetLogicalCPUID(u32 Node) ret = AMD_RB_C2; break; case 0x10043: + case 0x10053: ret = AMD_RB_C3; break; case 0x10062:
According to my research the RB C3 ist closest to my BL C3 and with this patch soft_reset seems to work now. The other problems still remains, ie
- seabios payload: no gfx output, but postcode is F8 - grub2 payload, coreboot initialized option ROM: infinte reset loop (but now "warm start" and cold start behaviour is identical).
I might try putting in a delay for the post code function, so I can wrtie down the last post code in the reset loop...
Cheers,
Prakash