Thomas,
from i3100_northbridge.patch:
Index: a/src/northbridge/intel/i3100/raminit.c
/* The memory is now setup, use it */+#if USE_DCACHE_RAM == 0 cache_lbmem(MTRR_TYPE_WRBACK); +#endif }
Could you explain why you had to add this?
After that I'll Ack this patch.
I've refactored two of your patches so that they use svn cp from kontron and model_6fx sources to show the differences. If you based your work on different sources, let me know.
My comments: There is some #if 0 code in acpi_tables. Will it ever be enabled? If not, remove it.
I'm confused why we need eagleheights_fixups. Can we remove it?
Index: svn/src/cpu/intel/model_1067x/cache_as_ram_post.c =================================================================== --- svn.orig/src/cpu/intel/model_1067x/cache_as_ram_post.c +++ svn/src/cpu/intel/model_1067x/cache_as_ram_post.c @@ -50,9 +50,9 @@ "wrmsr\n" "movl $MTRRphysMask_MSR(1), %ecx\n" "wrmsr\n" -#endif
"movb $0x33, %al\noutb %al, $0x80\n" +#endif #ifdef CLEAR_FIRST_1M_RAM "movb $0x34, %al\noutb %al, $0x80\n" /* Enable Write Combining and Speculative Reads for the first 1MB */ @@ -120,7 +120,7 @@ "movb $0x3b, %al\noutb %al, $0x80\n"
/* Enable prefetchers */ - "movl $0x01a0, %eax\n" + "movl $0x01a0, %ecx\n" "rdmsr\n" "andl $~((1 << 9) | (1 << 19)), %eax\n" "andl $~((1 << 5) | (1 << 7)), %edx\n"
These changes were surprising. Is there a bug in the original code?
Thanks, Myles