the following patch was just integrated into master: commit 510171e23bc6beaf502b0549e6ee446e47860715 Author: Martin Roth martin.roth@se-eng.com Date: Mon Feb 18 21:42:18 2013 -0700
Tyan S8226: Fix integer truncated warning
Fix Warning: sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal large integer implicitly truncated to unsigned type [-Woverflow]
The issue here was that an 8 bit value was being placed into a 2-bit bitfield.
$ more src/vendorcode/amd/cimx/sb700/SBTYPE.h […] UINT32 AzaliaSdin0 :2; //6 UINT32 AzaliaSdin1 :2; //8 UINT32 AzaliaSdin2 :2; //10 UINT32 AzaliaSdin3 :2; //12 $ more src/mainboard/tyan/s8226/sb700_cfg.h […] * SDIN0 is define at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin * SDIN1 is define at BIT2 & BIT3 * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN 0x2A #endif […] $ more src/mainboard/tyan/s8226/sb700_cfg.c […] sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; […]
The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly – I believe the original intent of this value was to enable the SDIN pins 0, 1, & 2. Because it was getting truncated as it was put into AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled.
I am leaving only SDIN0 enabled at this point to as not change the actual behavior on the platform.
Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34 Signed-off-by: Martin Roth martin.roth@se-eng.com Reviewed-on: http://review.coreboot.org/2452 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin dave.frodin@se-eng.com Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org
Build-Tested: build bot (Jenkins) at Tue Feb 19 12:01:31 2013, giving +1 Reviewed-By: Stefan Reinauer stefan.reinauer@coreboot.org at Tue Feb 19 23:44:48 2013, giving +2 See http://review.coreboot.org/2452 for details.
-gerrit