Re: [coreboot] patch: unshare pci operations

[Marc Jones]

Stefan Reinauer wrote:
> Here's the memory map of the low meg on one of my boxes running coreboot:
>      * 0x00000000 - 0x000003ff      Real Mode IVT
>      * 0x00000020 - 0x0000019c      MP Table (XXX conflict?)
>      * 0x00000400 - 0x000004ff      BDA (somewhat unused)
>      * 0x00000500 - 0x0000052f      Moved GDT
>      * 0x00000530 - 0x00000b64      coreboot table
>      * 0x00000c00 - 0x00000c9f      SMI communication
>      * 0x0007c000 - 0x0007dfff      OS boot sector (unused?)
>      * 0x0007e000 - 0x0007ffff      free to use
>      * 0x00080000 - 0x0009fbff      usable ram
>      * 0x0009fc00 - 0x0009ffff      EBDA (unused at the moment?)
>      * 0x000a0000 - 0x000bffff      VGA memory
>      * 0x000c0000 - 0x000cffff      VGA option rom
>      * 0x000d0000 - 0x000dffff      free for other option roms?
>      * 0x000e0000 - 0x000fffff      SeaBIOS? (XXX conflict?)
>      * 0x000f0000 - 0x000f03ff      PIRQ table
>      * 0x000f0400 - 0x000f66??      ACPI tables
>      * 0x000f66?? - 0x000f????      DMI tables

Seabios in E0000 is good. Mapping out where everything lives in F0000 is 
really good. The PIRQ table, DMI table, and the first part of the ACPI 
tables needs to be in F0000. A large part of the ACPI tables can be in 
the top of memory. We would need to add that region to E820 via the 
coreboot table. Maybe the coreboot table should be in F0000 too.

We should still have space left over to use for shared functions. Printk 
and lar functions might be the best candidates.

Marc