On Wed, Mar 12, 2014 at 9:07 AM, Peter Stuge peter@stuge.se wrote:
[on arm]
Why is it helpful or neccessary there?
It only matters if you like to have a dcache. Do you want a dcache? You must turn on paging.
On PPC, you have no choice, you can't turn off the soft TLBs on the new ones. So, you want PowerPC? It requires paging.
We will have to have it on x86_64.
Why is it neccessary there?
It only matters if you want to enter 64-bit mode. Want to enter 64-bit mode? turn on paging.
- MTRRs sure make for a lot of fuss.
- I wish we could do something simpler.
- Let's turn on paging, that would be simpler!
And, in fact, it is. It's far, far simpler. Just look at our last iteration of MTRR setup.
For the base identity map on x86-32, it's one page for 4G. For a map which locks out page 0, it's two pages.
I'm not saying that paging would not be simpler in some ways - I'm saying that it seems like a big change, introducing codebase-wide address indirection, for seemingly small gain of avoiding fuss with MTRRs.
No, there's much more to it than that, as I've explained.
And, again, we've had virtual addresses forever. That's what segmentation hardware does. We just had a 1:1 mapping. As we do on ARM today.
ron