Issue #492 has been reported by Martin Roth.
---------------------------------------- Other #492: Evaluate changes need to be made to support Intel's X86S ISA changes https://ticket.coreboot.org/issues/492
* Author: Martin Roth * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-05-28 ---------------------------------------- This past week, Intel announced a plan to boot directly to 64-bit mode[1]. While the timeline released with the announcement does't have any dates for the implementation, due to the huge impact this will have on coreboot, it seems appropriate to start looking at what changes will need to be made to support these changes to the ISA.
Changes currently listed: Changes in X86-S ISA consist of: - restricting the CPU to be always in paged mode - removing 32-bit ring 0, as well as vm86 mode. - removing ring 1 and ring 2 - removing 16-bit real and protected modes - removing 16-bit addressing - removing fixed MTRRs - removing user-level I/O and string I/O - removing CR0 Write-Through mode - removing legacy FPU control bits in CR0 - removing ring 3 interrupt flag control - removing obsolete CR access instruction - rearchitecting INIT/SIPI - adding a new mechanism to switch between 4- and 5-level page tables - removing XAPIC and only supporting x2APIC - removing APIC support for 8529 - removing the disabling of NX or SYSCALL or long mode in the EFER MSR - removing the #SS and #NP exceptions - supporting a subset of segmentation architecture, with the following conditions: o restricted to a subset of IDT event delivery o base only for FS, GS o base and limit for GDT, IDT, and TSS o no limit on data or code fetches in 32-bit mode (similar to 64-bit) o no AR or unusable selector checking on CS, DS, ES, FS, and GS on data or code fetches in any mode o restricted support for far call, far return, far jump, and IRET (like FRED).
1: https://web.archive.org/web/20230526070811/https://www.intel.com/content/www...