Hi All,
I tried to use coreboot to bringup Mohon Peak CRB with these 2 package from Intel (doc no. are 526100 & 526101). one is 526100_RANGELEY_CB_POSTGOLD_001_20131218.tar.gz, and the other is 526101_RANGELEY_FSP_POSTGOLD_002_20140402.zip.
I followed the guide within the package, successfully built a coreboot.rom, using dediprog to flash the board, then power on is ok, but the post code stopped at C0 which means 'POST_SECUROM_SECBOOT_START' defined in file './src/include/console/post_codes.h'
#define POST_SECUROM_SECBOOT_START (0x0C0) #define POST_SECUROM_BOOTSRCSETUP (0x0C1) #define POST_SECUROM_REMAP_FAIL (0x0C2) -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) #define POST_SECUROM_DCACHESETUP (0x0C4) -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) #define POST_SECUROM_ICACHESETUP (0x0C6) -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) #define POST_SECUROM_PLATFORMSETUP (0x0C9) #define POST_SECUROM_SIGCHECKBIOS (0x0CA) -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) -#define POST_SECUROM_PASS (0x0CC) -#define POST_SECUROM_FAIL
is there anybody see this before, what does this postcode mean?
Thanks
maypark01@163.com