[coreboot] Re: Braswell FPS memory init problems

[Frans Hendriks]

Hi Michal,

We have implemented coreboot on Braswell SoC (Pentium N3170) using SPD.

Did you verify the UDP fields: PcdMemoryTypeEnable, PcdMemorySpdPtr PcdMemChannel0Config and 
PcdMemChannel1Config?

Do you have some coreboot/FSP logging?

Best regards,
Frans Hendriks
Eltan B.V.

-----Original Message-----
From: Michal Zygowski [mailto:[e-mail]] 
Sent: maandag 28 januari 2019 15:48
To: [e-mail]
Cc: Piotr Król 
Subject: [coreboot] Braswell FPS memory init problems

Dear coreboot community,

I am experiencing problems with FSP Memory Init on Braswell SoCs. FSP Memory Init is not returning. I have following processors that fail:
Celeron J3060 and Celeron J3160; both have the same issue.

The platform has 1 SODIMM module on channel 0. I am feeding the UPD header with correct SPD, but still no luck. I have also tried FSP MR1 and MR2, but nothing works.

Is anyone here more experienced with Braswell platforms? Could You give me some advices?

Best regards,

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