* ali hagigat hagigatali@gmail.com [120214 18:48]:
I have initialized Intel 82815 SDRAM controller but for a special type of RAM without reading SPD registers. I know that DRP register is : 0xCC. I added the code to Coreboot.
I tested much and concluded that RAM has a problem in a way as you guys told me before. When i change the hardwaremain() , even adding some code which are bypassed, the results of the post code numbers become different!
I do not know what to do! c_start.S is OK and it is executed and the program starts executing hardwaremain() but adding code to the hardwaremain() any where seems to disorder printed post code values.
Is there any interrupt or timer set immediately after hardwaremain()?
I checked coreboot_ram in build/. The assembly code of hardwaremian() seems OK.
void sdram_enable(void) { asm("pushal"); asm("push %eax"); asm("push %ebx"); asm("push %ecx"); asm("push %edx"); asm("push %esi"); asm("push %edi"); asm("push %esp"); asm("push %ebp"); asm("pushfl"); asm("jmp firstlbl"); asm("mov %ax, %ax"); asm("nop");
[..]
There's a number of things wrong with this approach:
* if you don't use asm volatile instead of asm, gcc is free to reorder any of those statements as it sees fit.
* you need to put all of the code in one asm volatile statement, or gcc will attempt to clean up after each of the statements or overwrite registers as it sees fit.
But generally, I suggest you rewrite this in C, so it's a lot more readable...
Stefan