I'm trying to get coreboot up and running on an Intel RVP15 CRB, which is the same as the RVP7 except that the RVP15 has DDR4 memory instead of DDR3.
There is a mainboard solution for the RVP7 in coreboot. However, the current KabyLake FSP published on GitHub doesn't seem like it's the right FSP for the SkyLake-U/KabyLake-U. If nothing else, there's a problem with that FSP such that the signature in the FSP-M UPD header does not match the signature in the corresponding header files, so when the FSP 2.0 driver in coreboot goes to check that they are a match, execution dies right there.
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
die("Invalid FSPM signature!\n");
(coreboot/src/drivers/intel/fsp2_0/memory_init.c, in function do_fsp_memory_init)
I don't want to bypass that check in the code in case the FSP posted to GitHub isn't the right FSP for this particular SoC.
Obviously, somebody at Intel has the right FSP that works for these boards in order to validate that the coreboot implementation worked prior to upstreaming it to the repo. I'm just not sure how to get the right one so that I can get this booting.
Furthermore, I have yet to get the serial console working on the DB-9 serial port. I have the jumpers on the board configured to connect it to UART #2, and configured in coreboot accordingly, but I get nothing for console output.
Any help would be most appreciated!
Thanks,
- Jay
Jay Talbott Principal Consulting Engineer SysPro Consulting, LLC 3057 E. Muirfield St. Gilbert, AZ 85298 (480) 704-8045 (480) 445-9895 (FAX) mailto:JayTalbott@sysproconsulting.com JayTalbott@sysproconsulting.com
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