Hi,
On Sat, Jun 16, Corey Osgood wrote:
Great to hear! Now the question is, why is the baud rate being doubled? And is it doubled for all baud rates? Or, you can ignore it for now and get to work on ram init ;) Good luck!
I think it is double for all baudrates, because now I've configured 57600 Baud in Config.lb and 115200 in minicom.
Now I'am staying at the point point, but doesn't know who to do ram_init. The message "SDRAM is up" isn't shown.
There is one 512MB DIMM in my board:
here my auto.c
--snip-- #define ASSEMBLY 1 #define ASM_CONSOLE_LOGLEVEL 8
#include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" #include "southbridge/intel/i82801xx/i82801xx_reset.c" #include "northbridge/intel/i855pm/raminit.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/i855pm/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
static void memreset_setup(void) { }
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ }
static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); }
#include "northbridge/intel/i855pm/raminit.c" #include "northbridge/intel/i855pm/reset_test.c" #include "sdram/generic_sdram.c"
static void main(unsigned long bist) {
static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 1), .channel0 = { (0xa<<3)|0, 0 }, }, };
if (bist == 0) { early_mtrr_init(); enable_lapic(); }
/* Setup the console */ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); print_debug("Hello world\n\r"); report_bist_failure(bist); enable_smbus (); sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); print_debug("SDRAM is up.\r\n"); dump_pci_device(PCI_DEV(0, 0, 0)); } --snip--
--snip-- LinuxBIOS-2.0.0.0Fallback Sa 16. Jun 08:24:39 CEST 2007 starting... Hello world SMBus controller enabled Ram1.00 00000040 <-04030201 00000070 <-00000000 00000080 <-00af0031 PCI: 00:02.00 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 03 04 00 00 00 00 00 00 00 00 00 00 00 00 50: 77 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 25 44 00 18 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 00 00 06 00 00 00 64 25 00 00 00 00 00 00 80: 31 00 af 00 00 00 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 45 f0 3e 9a 37 08 d6 80 a0: 00 00 00 00 00 80 03 24 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 58 2b 13 01 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ram2.00 Reading SPD data... spd_detect_dimms: 00000000 00000001 00000002 00000003 setting based on SPD data... page size =00000010 00000010 spd_detect_dimms: spd_detect_dimms: ref rate index:02 done returned size log 2 in bits is :0000001f dimm size =0000001f 00000000 Write size 08 to 40 PCI: 00:02.00 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 08 08 08 08 00 00 00 00 00 00 00 00 00 00 00 00 50: 70 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 25 44 00 2a 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 01 00 00 06 00 00 00 64 25 00 00 00 00 00 00 80: 31 00 af 00 00 00 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 45 f0 3e 9a 37 08 d6 80 a0: 00 00 00 00 00 80 03 24 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 18 59 3b 02 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ram3 Ram Enable 1 00000000PCI: 00:02.00 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 08 08 08 08 00 00 00 00 00 00 00 00 00 00 00 00 50: 70 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 25 44 00 2a 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 01 00 00 06 00 00 00 64 25 00 00 00 00 00 00 80: 31 00 af 00 00 00 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 45 f0 3e 9a 37 08 d6 80 a0: 00 00 00 00 00 80 03 24 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 e4 38 ee 02 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ram Enable 2 PCI: 00:00.00 00: 86 80 80 35 06 00 90 00 02 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 81 00 00 00 00 00 00 00 00 02 28 00 0e 50: 00 00 30 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 02 09 00 00 10 60 00 00 00 00 00 00 00 00 00 00 80: 02 00 00 a4 00 00 00 80 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 f0 e9 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 Ram Enable 3 P:10 R:11 R:00000000
LinuxBIOS-2.0.0.0Fallback Sa 16. Jun 08:24:39 CEST 2007 starting... Hello world SMBus controller enabled Ram1.00 00000040 <-04030201 00000070 <-00000000 00000080 <-00af0031 PCI: 00:02.00 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 03 04 00 00 00 00 00 00 00 00 00 00 00 00 50: 77 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 25 44 00 18 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 00 00 06 00 00 00 64 25 00 00 00 00 00 00 80: 31 00 af 00 00 00 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 45 f0 3e 9a 37 08 d6 80 a0: 00 00 00 00 00 80 03 24 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 d8 38 13 01 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ram2.00 Reading SPD data... spd_detect_dimms: 00000000 00000001 00000002 00000003 setting based on SPD data... page size =00000010 00000010 spd_detect_dimms: spd_detect_dimms: ref rate index:02 done returned size log 2 in bits is :0000001f dimm size =0000001f 00000000 Write size 08 to 40 PCI: 00:02.00 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 08 08 08 08 00 00 00 00 00 00 00 00 00 00 00 00 50: 70 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 25 44 00 2a 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 01 00 00 06 00 00 00 64 25 00 00 00 00 00 00 80: 31 00 af 00 00 00 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 45 f0 3e 9a 37 08 d6 80 a0: 00 00 00 00 00 80 03 24 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 d4 23 3b 02 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ram3 Ram Enable 1 00000000PCI: 00:02.00 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 08 08 08 08 00 00 00 00 00 00 00 00 00 00 00 00 50: 70 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 25 44 00 2a 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 01 00 00 06 00 00 00 64 25 00 00 00 00 00 00 80: 31 00 af 00 00 00 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 45 f0 3e 9a 37 08 d6 80 a0: 00 00 00 00 00 80 03 24 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 70 19 ee 02 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ram Enable 2 PCI: 00:00.00 00: 86 80 80 35 06 00 90 00 02 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 81 00 00 00 00 00 00 00 00 02 28 00 0e 50: 00 00 30 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 02 09 00 00 10 60 00 00 00 00 00 00 00 00 00 00 80: 02 00 00 a4 00 00 00 80 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 f0 e9 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 Ram Enable 3 P:10 R:11 --snip--