amd_fam10_ht_sb_only.diff: I am not sure about this patch. Not sure to add signed-off-by line. Don't ack it before review it and say something.
My board is Fam10 + 1 HT SouthBridge. It is close to dbm690t. So I set HT_CHAIN_UNITID_BASE as 0 and HT_CHAIN_END_UNITID_BASE as 1, even though I don't know well what they actually are. Base on currently fam10 code, I have skip some code, otherwise the HT link can not be set up correctly. It is pretty like a workaround and my board can work in 1.8GHz (HT3). Doesn't the code in repository cover the mode of one HT processor + 1 HT SB device?
Index: src/northbridge/amd/amdht/h3finit.c =================================================================== --- src/northbridge/amd/amdht/h3finit.c (revision 503) +++ src/northbridge/amd/amdht/h3finit.c (working copy) @@ -1104,6 +1104,7 @@ AmdPCIRead(currentPtr, &temp); } while (!IS_HT_SLAVE_CAPABILITY(temp));
+#if (HT_CHAIN_UNITID_BASE != 0) AmdPCIReadBits(currentPtr, 25, 21, &unitIDcnt); if ((unitIDcnt + currentBUID > 31) || ((secBus == 0) && (unitIDcnt + currentBUID > 24))) { @@ -1145,7 +1146,7 @@ STOP_HERE; break; } - +#endif AmdPCIReadBits(currentPtr, 26, 26, &temp); pDat->PortList[pDat->TotalLinks*2+1].Link = (u8)temp; pDat->PortList[pDat->TotalLinks*2+1].Pointer = currentPtr; @@ -1156,6 +1157,11 @@ depth++; pDat->TotalLinks++; currentBUID += unitIDcnt; +#if HT_CHAIN_UNITID_BASE == 0 + STOP_HERE; + break; +#endif + } if (pDat->HtBlock->AMD_CB_EventNotify) {
****************************************************************** amd_fam10_mct_am2_rough.diff: The original code was pretty weird. It definitely can not be build correctly. This patch is only about building error.
The mctardk4 seems to be for AM2. Based on the code and this patch, the memory seems to work but is unstable and unbearably slow. I need to dig it more.
Since I am confused about this, it is not a signed-off-by patch.
Index: src/northbridge/amd/amdmct/mct/mctardk4.c =================================================================== --- src/northbridge/amd/amdmct/mct/mctardk4.c (revision 503) +++ src/northbridge/amd/amdmct/mct/mctardk4.c (working copy) @@ -25,7 +25,7 @@
void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct) - +{ print_tx("dct: ", dct); print_tx("Speed: ", pDCTstat->Speed);
@@ -66,42 +66,43 @@ */
static const u8 Table_ATC_ODC_D_Bx[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 - 0FFh + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, + 0xFF +};
static const u8 Table_ATC_ODC_D_Ax[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, 0xFF };
static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u32 *CMDmode); + u32 *CMDmode) { u8 *p;
@@ -168,5 +169,5 @@ } p+=10; } while (0xFF == *p); - + } }
************************************************************
-----Original Message----- From: Marc Jones [mailto:marcj303@gmail.com] Sent: Friday, June 19, 2009 12:17 PM To: Bao, Zheng Cc: coreboot@coreboot.org Subject: Re: Does the fam10 code work now?
On Thu, Jun 18, 2009 at 9:07 PM, Bao, ZhengZheng.Bao@amd.com wrote:
- The processor I work on is Socket AM2r2. Is it supported?
I only used socket F. You might need to to make some adjustments for AM2.
- The board I work on is Fam10(AM2r2)+RS780+SB700, somehow like
dbm690t. what is the configuration in Option.lb. HT_CHAIN_UNITID_BASE? HT_CHAIN_END_UNITID_BASE? I am still confused about these settings.
It depends on the chipset and board configuration. You should be able to set that the same as the dbm690T.
- If the HT can not be configured to HT3 mode, can the MCT be set at
high speed?
I think it should work at HT1 speeds. I don't know how closely they are really connected. The HT just needs to be setup before memory. Is there more than one CPU? Can the 780 do HT3?
Marc