Hello Punit and Paul,
On Sat, Jul 30, 2016 at 09:02:24PM +0200, Paul Menzel via coreboot wrote:
Dear Punit,
Am Samstag, den 30.07.2016, 15:35 +0530 schrieb punit vara:
I am new to coreboot
Welcome to coreboot.
and would like to contribute to "coreboot on the open source Berkeley RISC V processor". Is it available to work ? I am current GSOC student under RTEMS org developing BSP for beagle bone black for RTEMS RTOS. If I can work on this project Please what are the things I need to set up to work on?
Sure. As coreboot is free software you of course can work on it. There are already people working on it. Mainly Jonathan Neuschäfer as you can see from the blog posts about his GSoC progress [1] and his change sets [2] (`git log --author=Neusch`).
So I suggest, to get familiar with that work, build the current state and get it running with QEMU. Then just dive in the things you are interested in.
QEMU doesn't really work anymore with current versions of the RISC-V tools, and probably won't until it is updated to version 1.9 of the RISC-V Privileged Architecture Specification[1]. There are some instructions on how to run coreboot on RISC-V available in the coreboot wiki[2]. Spike has better support in coreboot, but it still doesn't work well enough to boot Linux (something's wrong with the page tables and Spike doesn't implement any block devices AFAICS).
Regards, Jonathan Neuschäfer
[1]: https://riscv.org/specifications/privileged-isa/ [2]: https://www.coreboot.org/Board:emulation/spike-riscv