On Thu, Feb 21, 2019 at 5:44 AM Matt B matthewwbradley6@gmail.com wrote:
... and the iGPU will not be initialized. Is this correct?
Integrated GPU will be initialized and will be working perfectly even if we are not doing the VFCT for it! :-) Aside from one angry "[drm:radeon_get_bios [radeon]] *ERROR* ACPI VFCT image header truncated" message at Linux kernel logs (see the end of this message) we have not noticed any downsides from doing the ACPI VFCT tables for G505S discrete GPU only instead of integrated.
So both integrated and discrete GPU of G505S are now working fine with these three coreboot patches ( 31448 / 31449 / 31450 ). Although it is a bit disappointing to see they have not been received well, I will continue working on them and hopefully they would be merged to coreboot master one day. Meanwhile I could write a small script that will be securely downloading and applying them, just like we are already doing for the "15h / 16h updated microcode" changes.
Best regards, Mike Banon
... [drm] radeon kernel modesetting enabled. checking generic (d0000000 420000) vs hw (d0000000 10000000) fb: switching to radeondrmfb from VESA VGA Console: switching to colour dummy device 80x25 [drm] initializing kernel modesetting (ARUBA 0x1002:0x990B 0x1002:0x990B 0x00). [drm:radeon_get_bios [radeon]] *ERROR* ACPI VFCT image header truncated ATOM BIOS: 113 radeon 0000:00:01.0: VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used) radeon 0000:00:01.0: GTT: 1024M 0x0000000020000000 - 0x000000005FFFFFFF [drm] Detected VRAM RAM=512M, BAR=256M [drm] RAM width 64bits DDR [TTM] Zone kernel: Available graphics memory: 7977572 kiB [TTM] Zone dma32: Available graphics memory: 2097152 kiB [TTM] Initializing pool allocator [TTM] Initializing DMA pool allocator [drm] radeon: 512M of VRAM memory ready [drm] radeon: 1024M of GTT memory ready. [drm] Loading ARUBA Microcode [drm] Internal thermal controller without fan control [drm] radeon: dpm initialized [drm] Found VCE firmware/feedback version 50.0.1 / 17! [drm] GART: num cpu pages 262144, num gpu pages 262144 [drm] PCIE GART of 1024M enabled (table at 0x00000000001D6000). radeon 0000:00:01.0: WB enabled radeon 0000:00:01.0: fence driver on ring 0 use gpu addr 0x0000000020000c00 and cpu addr 0x (ptrval) radeon 0000:00:01.0: fence driver on ring 5 use gpu addr 0x0000000000075a18 and cpu addr 0x (ptrval) radeon 0000:00:01.0: fence driver on ring 6 use gpu addr 0x0000000020000c18 and cpu addr 0x (ptrval) radeon 0000:00:01.0: fence driver on ring 7 use gpu addr 0x0000000020000c1c and cpu addr 0x (ptrval) radeon 0000:00:01.0: fence driver on ring 1 use gpu addr 0x0000000020000c04 and cpu addr 0x (ptrval) radeon 0000:00:01.0: fence driver on ring 2 use gpu addr 0x0000000020000c08 and cpu addr 0x (ptrval) radeon 0000:00:01.0: fence driver on ring 3 use gpu addr 0x0000000020000c0c and cpu addr 0x (ptrval) radeon 0000:00:01.0: fence driver on ring 4 use gpu addr 0x0000000020000c10 and cpu addr 0x (ptrval) [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [drm] Driver supports precise vblank timestamp query. radeon 0000:00:01.0: radeon: MSI limited to 32-bit radeon 0000:00:01.0: radeon: using MSI. [drm] radeon: irq initialized. [drm] ring test on 0 succeeded in 2 usecs [drm] ring test on 3 succeeded in 3 usecs [drm] ring test on 4 succeeded in 3 usecs ring test on 5 succeeded in 2 usecs [drm] UVD initialized successfully. [drm] ring test on 6 succeeded in 17 usecs [drm] ring test on 7 succeeded in 4 usecs [drm] VCE initialized successfully. [drm] ib test on ring 0 succeeded in 0 usecs [drm] ib test on ring 3 succeeded in 0 usecs [drm] ib test on ring 4 succeeded in 0 usecs ...
On Mon, Feb 18, 2019 at 10:02 AM Mike Banon mikebdp2@gmail.com wrote:
Great news! /u/QubesN00b from Reddit has flashed this dGPU build to his "no-dGPU" G505S and everything is working fine for him :D