On Wed, Feb 11, 2009 at 7:36 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Improve mainboard.c comments for DBM690T and Pistachio. Fix reference to documentation. Use __FUNCTION__ instead of hardcoding function names in printk messages.
from: http://gcc.gnu.org/onlinedocs/gcc/Function-Names.html
__FUNCTION__ is another name for __func__. Older versions of GCC recognize only this name. However, it is not standardized. For maximum portability, we recommend you use __func__, but provide a fallback definition with the preprocessor:
#if __STDC_VERSION__ < 199901L # if __GNUC__ >= 2 # define __func__ __FUNCTION__ # else # define __func__ "<unknown>" # endif #endif
I don't know if it matters too much. I like __func__ better personally.
Comments inline.
Acked-by: Myles Watson mylesgw@gmail.com
Myles
No functional changes.
I'm slowly getting to the point where adding another RS690 board is really easy and needs almost no changes to the existing target.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c (Revision 3936) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c (Arbeitskopie) @@ -49,11 +49,11 @@
- It has a pin named LOW_POWER to enable it into LOW POWER state.
- In order to run NIC, we should let it out of Low power state. This pin is
- controlled by GPM8.
-* RPR4.2.3 GPM as GPIO +* RRG4.2.3 GPM as GPIO
- GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
- I/O C50, C51, C52, PM I/O94, 95, 96.
-* RPR4.2.3.1 GPM pins as Input -* RPR4.2.3.2 GPM pins as Output +* RRG4.2.3.1 GPM pins as Input +* RRG4.2.3.2 GPM pins as Output
- The R77 (on BRASS) / R81 (on Bronze) is not load!
- So NIC can work whether this function runs.
********************************************************/ @@ -191,18 +191,18 @@ sm_dev->path.u.pci.devfn, 0x41, byte);
/* set GPM5 as input */
/* step1: set index register 0C50h to 13h (miscellaneous control) */
/* set index register 0C50h to 13h (miscellaneous control) */
What's gained by taking out the step numbers?
outb(0x13, 0xC50); /* CMIndex */
/* step2: set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
/* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */ byte = inb(0xC51); /* CMData */ byte &= 0x3f; byte |= 1 << 6; outb(byte, 0xC51);
/* step3: set GPM port 0C52h appropriate bits to 1 to tri-state the GPM port */
/* set GPM port 0C52h bit 5 to 1 to tri-state the GPM port */ byte = inb(0xc52); /* GpmPort */ byte |= 1 << 5; outb(byte, 0xc52);
/* step4: set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
/* set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */ byte = inb(0xc51); byte &= 0x3f; outb(byte, 0xc51);@@ -282,14 +282,14 @@ /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); printk_info
("pistachio_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",msr.lo, msr.hi);
("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",__FUNCTION__, msr.lo, msr.hi);
You could move this onto the same line as the prink now.
/* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); printk_info
("pistachio_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",msr2.lo, msr2.hi);
("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",__FUNCTION__, msr2.lo, msr2.hi);
Same here.
switch (msr.lo) { case 0x10000000: /* 256M system memory */@@ -310,8 +310,8 @@ }
uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk_info("pistachio_enable: uma size 0x%08x, memory start 0x%08x\n",uma_memory_size, uma_memory_start);
printk_info("%s: uma size 0x%08x, memory start 0x%08x\n",__FUNCTION__, uma_memory_size, uma_memory_start); /* TODO: TOP_MEM2 */#else Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Revision 3936) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -49,8 +49,8 @@ /********************************************************
- dbm690t uses a BCM5789 as on-board NIC.
- It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin -* is controlled by sb600 GPM3. +* In order to run NIC, we should let it out of Low power state. This pin is +* controlled by sb600 GPM3.
- RRG4.2.3 GPM as GPIO
- GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
- I/O C50, C51, C52, PM I/O94, 95, 96.
@@ -63,22 +63,27 @@
printk_info("enable_onboard_nic.\n");
outb(0x13, 0xC50);
/* set index register 0C50h to 13h (miscellaneous control) */outb(0x13, 0xC50); /* CMIndex *//* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */ byte = inb(0xC51); byte &= 0x3F; byte |= 0x40; outb(byte, 0xC51);/* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */ byte = inb(0xC52); byte &= ~0x8; outb(byte, 0xC52);/* set CM data register 0C51h bits [7:6] to 10b to set Output state control */ byte = inb(0xC51); byte &= 0x3F; byte |= 0x80; /* 7:6=10 */ outb(byte, 0xC51);/* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */ byte = inb(0xC52); byte &= ~0x8; outb(byte, 0xC52);@@ -205,14 +210,14 @@ /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); printk_info
("dbm690t_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",msr.lo, msr.hi);
("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",__FUNCTION__, msr.lo, msr.hi);
Same here.
/* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); printk_info
("dbm690t_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",msr2.lo, msr2.hi);
("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",__FUNCTION__, msr2.lo, msr2.hi);
and here.
switch (msr.lo) { case 0x10000000: /* 256M system memory */@@ -233,8 +238,8 @@ }
uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk_info("dbm690t_enable: uma size 0x%08x, memory start 0x%08x\n",uma_memory_size, uma_memory_start);
printk_info("%s: uma size 0x%08x, memory start 0x%08x\n",__FUNCTION__, uma_memory_size, uma_memory_start); /* TODO: TOP_MEM2 */#else
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c (Revision 3936) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c (Arbeitskopie) @@ -49,11 +49,11 @@
- It has a pin named LOW_POWER to enable it into LOW POWER state.
- In order to run NIC, we should let it out of Low power state. This pin is
- controlled by GPM8.
-* RPR4.2.3 GPM as GPIO +* RRG4.2.3 GPM as GPIO
- GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
- I/O C50, C51, C52, PM I/O94, 95, 96.
-* RPR4.2.3.1 GPM pins as Input -* RPR4.2.3.2 GPM pins as Output +* RRG4.2.3.1 GPM pins as Input +* RRG4.2.3.2 GPM pins as Output
- The R77 (on BRASS) / R81 (on Bronze) is not load!
- So NIC can work whether this function runs.
********************************************************/ @@ -191,18 +191,18 @@ sm_dev->path.u.pci.devfn, 0x41, byte);
/* set GPM5 as input */
/* step1: set index register 0C50h to 13h (miscellaneous control) */
/* set index register 0C50h to 13h (miscellaneous control) */ outb(0x13, 0xC50); /* CMIndex */
/* step2: set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
/* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */ byte = inb(0xC51); /* CMData */ byte &= 0x3f; byte |= 1 << 6; outb(byte, 0xC51);
/* step3: set GPM port 0C52h appropriate bits to 1 to tri-state the GPM port */
/* set GPM port 0C52h bit 5 to 1 to tri-state the GPM port */ byte = inb(0xc52); /* GpmPort */ byte |= 1 << 5; outb(byte, 0xc52);
/* step4: set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
/* set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */ byte = inb(0xc51); byte &= 0x3f; outb(byte, 0xc51);@@ -282,14 +282,14 @@ /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); printk_info
("pistachio_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",msr.lo, msr.hi);
("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",__FUNCTION__, msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); printk_info
("pistachio_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",msr2.lo, msr2.hi);
("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",__FUNCTION__, msr2.lo, msr2.hi); switch (msr.lo) { case 0x10000000: /* 256M system memory */@@ -310,8 +310,8 @@ }
uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk_info("pistachio_enable: uma size 0x%08x, memory start 0x%08x\n",uma_memory_size, uma_memory_start);
printk_info("%s: uma size 0x%08x, memory start 0x%08x\n",__FUNCTION__, uma_memory_size, uma_memory_start); /* TODO: TOP_MEM2 */#else Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Revision 3936) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -49,8 +49,8 @@ /********************************************************
- dbm690t uses a BCM5789 as on-board NIC.
- It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin -* is controlled by sb600 GPM3. +* In order to run NIC, we should let it out of Low power state. This pin is +* controlled by sb600 GPM3.
- RRG4.2.3 GPM as GPIO
- GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
- I/O C50, C51, C52, PM I/O94, 95, 96.
@@ -63,22 +63,27 @@
printk_info("enable_onboard_nic.\n");
outb(0x13, 0xC50);
/* set index register 0C50h to 13h (miscellaneous control) */outb(0x13, 0xC50); /* CMIndex *//* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */ byte = inb(0xC51); byte &= 0x3F; byte |= 0x40; outb(byte, 0xC51);/* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */ byte = inb(0xC52); byte &= ~0x8; outb(byte, 0xC52);/* set CM data register 0C51h bits [7:6] to 10b to set Output state control */ byte = inb(0xC51); byte &= 0x3F; byte |= 0x80; /* 7:6=10 */ outb(byte, 0xC51);/* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */ byte = inb(0xC52); byte &= ~0x8; outb(byte, 0xC52);@@ -205,14 +210,14 @@ /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); printk_info
("dbm690t_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",msr.lo, msr.hi);
("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",__FUNCTION__, msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); printk_info
("dbm690t_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",msr2.lo, msr2.hi);
("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",__FUNCTION__, msr2.lo, msr2.hi); switch (msr.lo) { case 0x10000000: /* 256M system memory */@@ -233,8 +238,8 @@ }
uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk_info("dbm690t_enable: uma size 0x%08x, memory start 0x%08x\n",uma_memory_size, uma_memory_start);
printk_info("%s: uma size 0x%08x, memory start 0x%08x\n",__FUNCTION__, uma_memory_size, uma_memory_start); /* TODO: TOP_MEM2 */#else
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