the following patch was just integrated into master: commit fa8702cf2a30f32a2d9918548276e1b7b6ec0d2a Author: Jens Rottmann JRottmann@LiPPERTembedded.de Date: Mon Feb 18 19:40:33 2013 +0100
Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon
Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset code has been blindly copied even though it doesn't suit the Persimmon at all.
The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.)
However the Persimmon not only doesn't support this, it even needs these 3 pins for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all at once. Lane 3 is unconnected anyway.
This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D schematics.
Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7 Signed-off-by: Jens Rottmann JRottmann@LiPPERTembedded.de Reviewed-on: http://review.coreboot.org/2446 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge peter@stuge.se
Build-Tested: build bot (Jenkins) at Mon Feb 18 20:20:21 2013, giving +1 Reviewed-By: Peter Stuge peter@stuge.se at Mon Feb 18 22:49:38 2013, giving +2 See http://review.coreboot.org/2446 for details.
-gerrit