Ronald G. Minnich (rminnich@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2462
-gerrit
commit 1561ecb4291385934d32ebabeda8ad0f5d06c7a4 Author: Ronald G. Minnich rminnich@google.com Date: Wed Feb 20 09:24:29 2013 -0800
ARMV7: minor tweaks to inter-stage calling and payload handling.
Payloads, by design, can return. There's lots of mechanism in the payload code to support it, and the chooser payload relies on it. Hence, we should not mark the function call in exit_stage as noreturn.
Not all ARM have unified caches, and it's not always easy to tell what to do. So we are very paranoid. Before we call between stages, we should carefully flush the dcache to memory and invalidate the icache. This may be more than is necessary on all architectures but it doesn't really hurt for the most part.
So compile cache management code into all stages, and call the flush dcache/invalidate icache from all stages.
Change-Id: Ib9cc625c4dfd2d7d4b3c69a74686cc655a9d6484 Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- src/arch/armv7/lib/Makefile.inc | 3 +++ src/arch/armv7/stages.c | 16 +++++++++++++++- src/cpu/samsung/exynos5250/Makefile.inc | 2 ++ 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 391b6a5..388864a 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +bootblock-y += cache_v7.c +bootblock-y += cache-cp15.c
romstage-y += cache_v7.c romstage-y += cache-cp15.c @@ -14,6 +16,7 @@ ramstage-y += div64.S #ramstage-y += memcpy.S #ramstage-y += memset.S ramstage-y += syslib.c +ramstage-y += cache_v7.c
#FIXME(dhendrix): should this be a config option? romstage-y += eabi_compat.c diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index 05b3e1d..c37c1dd 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -32,14 +32,28 @@ */
#include <arch/stages.h> +#include <arch/armv7/include/common.h>
void stage_entry(void) { main(); }
+/* we had marked 'doit' as 'noreturn'. + * There is no apparent harm in leaving it as something we can return from, and in the one + * case where we call a payload, the payload is allowed to return. + * Hence, leave it as something we can return from. + */ void stage_exit(void *addr) { - __attribute__((noreturn)) void (*doit)(void) = addr; + void (*doit)(void) = addr; + /* make sure any code we installed is written to memory. Not all ARM have + * unified caches. + */ + flush_dcache_all(); + /* Because most stages copy code to memory, it's a safe and hygienic thing + * to flush the icache here. + */ + invalidate_icache_all(); doit(); } diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index c9a9341..33fcedc 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,6 +9,7 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c +bootblock-y += exynos_cache.c
romstage-y += clock.c romstage-y += clock_init.c @@ -28,6 +29,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += exynos_cache.c
#ramstage-$(CONFIG_SATA_AHCI) += sata.c